LM5109BMA/NOP
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National Semiconductor LM5109BMA/NOP

Manufacturer No:
LM5109BMA/NOP
Manufacturer:
National Semiconductor
Package:
Bulk
Description:
HALF BRIDGE BASED MOSFET DRIVER,
Delivery:
Payment:
iso14001
iso45001
iso9001
iso13485

Product Introduction

Overview

The LM5109BMA/NOP is a high-voltage, 1-A peak half-bridge gate driver designed and manufactured by Texas Instruments, although it may be listed under National Semiconductor in some catalogs due to historical reasons. This device is optimized for driving both the high-side and low-side N-channel MOSFETs in synchronous buck or half-bridge configurations. It features robust level shift technology, high-speed operation, and low power consumption, making it suitable for a variety of power management applications.

Key Specifications

SpecificationValueUnit
Peak Output Current1.0 A (Sink and Source)A
Bootstrap Supply VoltageUp to 108 V DCV
Propagation Times30 ns (Typical)ns
Rise and Fall Times15 ns (Typical for 1000-pF Load)ns
Propagation Delay Matching2 ns (Typical)ns
Undervoltage Lockout (UVLO)Typically 6.7 VV
Operating Temperature Range-40°C to 125°C°C
Package Type8-Pin SOIC and 8-Pin WSON
Input CompatibilityTTL and CMOS

Key Features

  • High-Side and Low-Side Driver: Drives both high-side and low-side N-channel MOSFETs in synchronous buck or half-bridge configurations.
  • High Peak Output Current: 1-A peak output current for both sink and source.
  • TTL and CMOS Compatibility: Inputs are compatible with independent TTL and CMOS thresholds.
  • Bootstrap Supply Voltage: Supports bootstrap supply voltage up to 108 V DC.
  • Fast Propagation Times: Typical propagation times of 30 ns.
  • Low Power Consumption: Designed for low power consumption.
  • Robust Level Shift Technology: Provides clean level transitions from control input logic to the high-side gate driver.
  • Undervoltage Lockout (UVLO): UVLO protection on both low-side and high-side power rails.

Applications

  • Synchronous Buck Converters: Ideal for driving MOSFETs in synchronous buck configurations.
  • Half-Bridge and Full-Bridge Configurations: Suitable for half-bridge and full-bridge power stages.
  • Power Management Systems: Used in various power management systems requiring high-speed and high-voltage gate driving.
  • Industrial and Automotive Systems: Applicable in industrial and automotive applications where robust and reliable gate driving is necessary.

Q & A

  1. What is the peak output current of the LM5109BMA/NOP?

    The peak output current is 1.0 A for both sink and source.

  2. What is the maximum bootstrap supply voltage for the LM5109BMA/NOP?

    The maximum bootstrap supply voltage is up to 108 V DC.

  3. What are the typical propagation times for the LM5109BMA/NOP?

    The typical propagation times are 30 ns.

  4. Is the LM5109BMA/NOP compatible with TTL and CMOS inputs?

    Yes, the inputs are compatible with both TTL and CMOS thresholds.

  5. What is the operating temperature range for the LM5109BMA/NOP?

    The operating temperature range is -40°C to 125°C.

  6. What types of packages are available for the LM5109BMA/NOP?

    The device is available in 8-pin SOIC and 8-pin WSON packages.

  7. Does the LM5109BMA/NOP have undervoltage lockout (UVLO) protection?

    Yes, it has UVLO protection on both the low-side and high-side power rails.

  8. What are the recommended bypass capacitors for the LM5109BMA/NOP?

    Texas Instruments recommends using a 100-nF ceramic surface-mount capacitor for high-frequency filtering and another surface-mount capacitor (220-nF to 10-µF) for IC bias requirements, both placed close to the VDD and GND pins.

  9. How should the bootstrap capacitor be selected and connected?

    The bootstrap capacitor should be a ceramic type with X7R dielectric, and it must be charged through an external high-voltage diode. The capacitor should be placed as close to the IC as possible.

  10. What are the key considerations for selecting external gate driver resistors?

    The external gate driver resistors should be selected to reduce ringing caused by parasitic inductances and capacitances and to limit the current coming out of the gate driver. Values typically range between 2 Ω and 10 Ω depending on the diode selection.

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