Overview
The NXP Layerscape LX2160SC72232B is a high-performance, 16-core processor based on the Arm Cortex-A72 architecture. This processor is part of the Layerscape family and is designed to offer low power consumption through FinFET process technology. It is ideal for demanding applications such as 5G packet processing, network function virtualization (NFV), and white-box switching.
Key Specifications
| Specification | Details |
|---|---|
| Cores | 16 Arm Cortex-A72 cores |
| Core Frequency | Up to 2.2 GHz |
| L1 Cache | 48KB instruction cache and 32KB data cache per core |
| L2 Cache | 8 MB shared L2 cache |
| L3 Cache | 8 MB Level 3 cache with ECC and On-Chip Memory (OCM) mode |
| Memory Controllers | Two 72-bit (64-bit + ECC) 3.2 GT/s DDR4 SDRAM memory controllers |
| Peripheral Interfaces | Two PCIe Gen 3.0 8-lane controllers, four PCIe Gen 3.0 4-lane controllers, four SATA 3.0 controllers, two USB 3.0 controllers with integrated PHY, two CAN modules, Flexible SPI and SPI controllers, eight I2C controllers, four UARTs, GPIO |
| Ethernet Interfaces | Up to 18 Ethernet MACs, support for various Ethernet standards including 10G-SXGMII, SGMII, XFI, SFI, 10GBase-KR, CAUI4, CAUI2, 25G-AUI, XLAUI4 |
| Package | 1517 ball BGA package |
Key Features
- High-performance Arm Cortex-A72 cores with up to 2.2 GHz frequency.
- Cache Coherent Interconnect Fabric up to 1500 MHz.
- Datapath acceleration architecture 2.0 (DPAA2) with packet parsing, classification, and distribution, cryptography acceleration, decompression/compression acceleration, and Queue Direct Memory Access (QDMA) engine.
- 24 SerDes lanes at up to 25 Gbps.
- Support for hardware virtualization and partitioning enforcement (ARM MMU-500) and global interrupt controller (ARM GIC-500).
- QorIQ platform trust architecture 3.0 with 256 KB on-chip RAM for trusted accesses.
- Energy-efficient support (802.3az) for Ethernet interfaces.
Applications
- 5G packet processing and network infrastructure.
- Network function virtualization (NFV) and software-defined networking (SDN).
- White-box switching and network appliances.
- Cloud and data center applications requiring high performance and low power consumption.
- Industrial automation and control systems.
Q & A
- What is the LX2160SC72232B processor based on?
The LX2160SC72232B is based on the Arm Cortex-A72 architecture.
- How many cores does the LX2160SC72232B have?
The LX2160SC72232B has 16 Arm Cortex-A72 cores.
- What is the maximum frequency of the LX2160SC72232B cores?
The cores can operate up to 2.2 GHz.
- What type of memory controllers does the LX2160SC72232B support?
The processor supports two 72-bit (64-bit + ECC) 3.2 GT/s DDR4 SDRAM memory controllers.
- What are some of the key peripheral interfaces supported by the LX2160SC72232B?
The processor supports PCIe Gen 3.0, SATA 3.0, USB 3.0, CAN, SPI, I2C, UART, and GPIO.
- What Ethernet standards does the LX2160SC72232B support?
The processor supports various Ethernet standards including 10G-SXGMII, SGMII, XFI, SFI, 10GBase-KR, CAUI4, CAUI2, 25G-AUI, and XLAUI4.
- What is the package type of the LX2160SC72232B?
The processor is packaged in a 1517 ball BGA package.
- What are some typical applications for the LX2160SC72232B?
Typical applications include 5G packet processing, NFV, white-box switching, cloud and data center applications, and industrial automation.
- Does the LX2160SC72232B support hardware virtualization?
Yes, it supports hardware virtualization and partitioning enforcement through ARM MMU-500 and global interrupt controller ARM GIC-500.
- What is the role of DPAA2 in the LX2160SC72232B?
DPAA2 (Datapath acceleration architecture 2.0) provides packet parsing, classification, and distribution, cryptography acceleration, decompression/compression acceleration, and Queue Direct Memory Access (QDMA) engine.
