Overview
The LS1046AXE8T1A is a highly integrated system-on-chip (SoC) designed by NXP USA Inc. as part of the QorIQ Layerscape family. This processor is tailored for high-performance, power-efficient applications, featuring four 64-bit Arm Cortex-A72 cores. Each core operates up to 1.8 GHz and is equipped with ECC-protected L1 and L2 cache memories, ensuring high reliability. The LS1046AXE8T1A is ideal for a variety of embedded applications, including enterprise routers, switches, linecard controllers, network attached storage, security appliances, and single board computers.
Key Specifications
Specification | Details |
---|---|
Cores | Four 64-bit Arm Cortex-A72 cores |
Core Frequency | Up to 1.8 GHz |
Cache Memory | 32 KB L1 data cache, 48 KB L1 instruction cache, 2 MB L2 cache |
Memory Controller | 32-bit/64-bit DDR4 SDRAM with ECC and interleaving support, up to 2.1 GT/s |
Package Type | 780-FCPBGA, 23 mm x 23 mm |
Peripheral Interfaces | Three PCI Express 3.0 controllers, one SATA 6 Gbit/s controller, up to two XFI (10 GbE) interfaces, up to five SGMII interfaces, three high-speed USB 3.0 controllers with integrated PHY |
Additional Interfaces | One Quad Serial Peripheral Interface (QSPI) controller, one Serial Peripheral Interface (SPI) controller, integrated flash controller (IFC), four I2C controllers, two 16550-compliant DUARTs, six low-power UARTs (LPUARTs) |
Data Path Acceleration Architecture (DPAA) | Packet parsing, classification, and distribution (FMan), queue management (QMan), hardware buffer management (BMan), cryptography acceleration (SEC) |
Operating Temperature | 0 to 105°C |
Key Features
- High-performance processing with four 64-bit Arm Cortex-A72 cores operating up to 1.8 GHz.
- ECC-protected L1 and L2 cache memories for high reliability.
- Data Path Acceleration Architecture (DPAA) for packet processing, queue management, buffer management, and cryptography acceleration.
- Support for high-speed interfaces including PCI Express 3.0, SATA 6 Gbit/s, XFI (10 GbE), SGMII, and USB 3.0 with integrated PHY.
- Integrated flash controller (IFC) supporting NAND and NOR flash.
- Multiple peripheral interfaces such as QSPI, SPI, I2C, DUARTs, and LPUARTs.
- Global programmable interrupt controller (GIC) and thermal monitoring unit (TMU).
Applications
- Enterprise routers and switches.
- Linecard controllers.
- Network attached storage.
- Security appliances.
- Virtual customer premise equipment (vCPE).
- Service provider gateways.
- Single board computers.
Q & A
- What is the LS1046AXE8T1A processor?
The LS1046AXE8T1A is a system-on-chip (SoC) designed by NXP USA Inc., featuring four 64-bit Arm Cortex-A72 cores.
- How many cores does the LS1046AXE8T1A have?
The LS1046AXE8T1A has four 64-bit Arm Cortex-A72 cores.
- What is the maximum operating frequency of the cores?
The cores operate up to 1.8 GHz.
- What type of memory controller does it support?
The LS1046AXE8T1A supports a 32-bit/64-bit DDR4 SDRAM memory controller with ECC and interleaving support, up to 2.1 GT/s.
- What are the key peripheral interfaces supported?
It supports three PCI Express 3.0 controllers, one SATA 6 Gbit/s controller, up to two XFI (10 GbE) interfaces, and three high-speed USB 3.0 controllers with integrated PHY.
- What is the Data Path Acceleration Architecture (DPAA)?
The DPAA includes acceleration for packet parsing, classification, and distribution (FMan), queue management (QMan), hardware buffer management (BMan), and cryptography acceleration (SEC).
- What is the operating temperature range of the LS1046AXE8T1A?
The operating temperature range is 0 to 105°C.
- What are some typical applications of the LS1046AXE8T1A?
Typical applications include enterprise routers, switches, linecard controllers, network attached storage, security appliances, and single board computers.
- What package type does the LS1046AXE8T1A use?
The LS1046AXE8T1A uses a 780-FCPBGA package, 23 mm x 23 mm.
- Does the LS1046AXE8T1A support secure boot and trust zone features?
Yes, it supports secure boot and trust zone features for enhanced security.