Overview
The 74LVC16373ADGG,112 is a 16-bit D-type transparent latch produced by Nexperia (formerly part of NXP Semiconductors). This device is designed to operate as two 8-bit transparent latches or a single 16-bit transparent latch. It features two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each controlling 8 bits of the latch. The device is notable for its wide supply voltage range, overvoltage tolerant inputs, and low power dissipation, making it suitable for a variety of applications in mixed 3.3 V and 5 V environments.
Key Specifications
| Type number | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC16373ADGG | 1.2 - 3.6 | TTL | ± 24 | 3.0 | Low | -40 ~ 125 | 82 | 2 | 37 | TSSOP48 |
Key Features
- Overvoltage tolerant inputs to 5.5 V
- Wide supply voltage range from 1.2 V to 3.6 V
- CMOS low power dissipation
- MULTIBYTE flow-through standard pinout architecture
- Multiple low inductance supply pins for minimum noise and ground bounce
- Direct interface with TTL levels
- Bus hold on the data inputs (74LVCH16373A only)
- IOFF circuitry provides partial Power-down mode operation
- ESD protection: HBM ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V, CDM ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Specified from -40 °C to +85 °C and -40 °C to +125 °C
Applications
The 74LVC16373ADGG is suitable for various applications, including:
- Mixed 3.3 V and 5 V environments where data translation is necessary
- Systems requiring low power consumption and high-speed data transfer
- Partial power-down applications where IOFF circuitry is beneficial
- Applications needing bus hold on data inputs to eliminate the need for external pull-up resistors
- General-purpose logic circuits where high impedance outputs are required
Q & A
- What is the primary function of the 74LVC16373ADGG?
The primary function is to act as a 16-bit D-type transparent latch, which can be used as two 8-bit latches or a single 16-bit latch.
- What is the supply voltage range for this device?
The supply voltage range is from 1.2 V to 3.6 V.
- What is the output drive capability of the 74LVC16373ADGG?
The output drive capability is ± 24 mA.
- Does the 74LVC16373ADGG have overvoltage tolerant inputs?
- What is the operating temperature range for this device?
The operating temperature range is from -40 °C to +125 °C.
- Does the 74LVC16373ADGG have ESD protection?
- What is the purpose of the IOFF circuitry in the 74LVC16373ADGG?
The IOFF circuitry provides partial Power-down mode operation, preventing backflow current when the device is powered down.
- Can the 74LVC16373ADGG be used in mixed 3.3 V and 5 V environments?
- What package type is the 74LVC16373ADGG available in?
The device is available in a TSSOP48 package.
- Does the 74LVC16373ADGG have bus hold on data inputs?
