Overview
The Intel MAX® II EPM570T100C5N is a Complex Programmable Logic Device (CPLD) from the MAX® II family, known for its instant-on, non-volatile architecture. This device is designed to provide low-cost, low-power solutions for a variety of applications, including bus bridging, I/O expansion, power-on reset (POR), and sequencing control. The EPM570T100C5N is part of the MAX® II family, which is based on a 0.18-µm, 6-layer-metal-flash process, ensuring fast propagation delay and clock-to-output times.
Key Specifications
| Specification | Value |
|---|---|
| Product Collection | MAX® II CPLD |
| Marketing Status | Launched |
| Launch Date | Q1'14 |
| Lithography | 180 nm |
| Equivalent Macrocells | 440 |
| Pin-to-pin Delay | 9 ns |
| User Flash Memory | 8 Kb |
| MultiVolt I/Os | 1.5, 1.8, 2.5, 3.3 V |
| I/O Power Banks | 2 |
| Maximum Output Enables | 160 |
| Package Options | M100, F100, M256, T100, F256, T144 |
| Package Size | 6mmx6mm, 11mmx11mm, 11mmx11mm, 16mmx16mm, 17mmx17mm, 22mmx22mm |
Key Features
- Boundary-scan JTAG: Yes, compliant with IEEE Std. 1149.1-1990.
- JTAG ISP: Yes, supports in-system programming.
- Fast Input Registers: Yes, enhancing performance.
- Programmable Register Power-up: Yes, for flexible initialization.
- JTAG Translator: Yes, for enhanced testing capabilities.
- Real-time ISP: Yes, allowing for real-time programming.
- MultiVolt I/Os: Supports 1.5, 1.8, 2.5, and 3.3 V logic levels.
- LVTTL/LVCMOS: Yes, compatible with various logic standards.
- Schmitt Triggers: Yes, enabling noise-tolerant inputs.
- Programmable Slew Rate: Yes, for customizable output characteristics.
- Programmable Pull-up Resistors: Yes, for flexible I/O configuration.
- Open-drain Outputs: Yes, supporting various output configurations.
- Bus Hold: Yes, maintaining signal integrity.
Applications
The Intel MAX® II EPM570T100C5N CPLD is suitable for a wide range of applications, including:
- Bus Bridging: Connecting different bus standards and protocols.
- I/O Expansion: Expanding the I/O capabilities of existing systems.
- Power-on Reset (POR) and Sequencing Control: Managing power-on sequences and reset functions.
- Device Configuration Control: Controlling the configuration of other devices in a system.
- Peripheral Component Interconnect (PCI) Applications: Compliant with PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 66 MHz.
Q & A
- What is the lithography of the MAX® II EPM570T100C5N?
The lithography of the MAX® II EPM570T100C5N is 180 nm.
- How many equivalent macrocells does the EPM570T100C5N have?
The EPM570T100C5N has 440 equivalent macrocells.
- What is the pin-to-pin delay of the EPM570T100C5N?
The pin-to-pin delay is 9 ns.
- Does the EPM570T100C5N support JTAG boundary-scan testing?
Yes, it supports JTAG boundary-scan testing compliant with IEEE Std. 1149.1-1990.
- What are the supported MultiVolt I/O levels for the EPM570T100C5N?
The device supports 1.5, 1.8, 2.5, and 3.3 V logic levels.
- Does the EPM570T100C5N have programmable slew rate and pull-up resistors?
Yes, it has programmable slew rate and pull-up resistors.
- Is the EPM570T100C5N compatible with PCI Local Bus Specification?
Yes, it is fully compliant with the PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 66 MHz.
- What is the user flash memory size of the EPM570T100C5N?
The user flash memory size is 8 Kb.
- Does the EPM570T100C5N support hot-socketing?
Yes, it supports hot-socketing.
- What are the package options available for the EPM570T100C5N?
The package options include M100, F100, M256, T100, F256, and T144.
