Overview
The ADSP-21479BBCZ-2A is a high-performance, low-power Digital Signal Processor (DSP) from Analog Devices Inc., part of the fourth generation SHARC Processor family. This DSP is optimized for high-performance audio processing and other demanding applications. It features a single-instruction, multiple-data (SIMD) core, supporting both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats. The ADSP-21479BBCZ-2A is particularly suited for battery-powered applications and environments requiring higher ambient operating temperatures, such as automotive audio and industrial control segments.
Key Specifications
| Specification | Details |
|---|---|
| Core Clock Speed | Up to 300 MHz (266 MHz for ADSP-21479BBCZ-2A) |
| On-Chip Memory | 5 Mbits of on-chip RAM, 4 Mbits of on-chip ROM |
| Accelerators | FIR, IIR, and FFT accelerators |
| External Memory Interface | 16-bit wide SDR SDRAM external memory interface |
| Peripheral Interfaces | Digital Applications Interface (DAI), S/P DIF Tx/Rx, 8-channel asynchronous sample rate converter |
| DMA Engine | Fully enhanced DMA engine including scatter/gather DMA, delay line DMA |
| Serial Ports | 8 serial ports (SPORTs) supporting I2S, left-justified sample pair, and TDM modes |
| PWM Channels | 16 Pulse Width Modulation (PWM) channels |
| Timers | 3 full-featured timers |
| Package Options | 196 ball CSP_BGA, 100 lead LQFP |
| Temperature Ranges | Commercial, Industrial, and Automotive temperature ranges |
Key Features
- High-performance SIMD core supporting 32-bit fixed-point and 32-/40-bit floating-point arithmetic
- Low power consumption, making it suitable for battery-powered applications
- Hardware-based filter accelerators (FIR, IIR, FFT) for enhanced system performance
- Variable Instruction Set Architecture (VISA) to reduce code size by 20% to 30% and increase memory availability
- Fully enhanced DMA engine with scatter/gather and delay line DMA capabilities
- Real-Time Clock (RTC) and Watch Dog Timer for system reliability
- Multiple peripheral interfaces including SPI, UART, and Two-Wire Interface
- Pin-compatible and code-compatible with all prior SHARC Processors
Applications
- Automotive audio systems: The low power and high performance make it ideal for automotive audio applications
- Industrial control: Suitable for industrial control segments where low power is a requirement
- High-quality audio processing: Optimized for high-performance audio processing
- Medical imaging: Supports applications in medical imaging
- Communications: Used in various communication systems
- Military and test equipment: Applicable in military and test equipment applications
- 3D graphics and speech recognition: Supports 3D graphics and speech recognition applications
- Motor control and imaging: Used in motor control and imaging applications
Q & A
- What is the core clock speed of the ADSP-21479BBCZ-2A?
The core clock speed of the ADSP-21479BBCZ-2A is up to 266 MHz, with a maximum of 300 MHz for the ADSP-21479 series
- How much on-chip memory does the ADSP-21479BBCZ-2A have?
The ADSP-21479BBCZ-2A has 5 Mbits of on-chip RAM and 4 Mbits of on-chip ROM
- What type of accelerators does the ADSP-21479BBCZ-2A include?
The ADSP-21479BBCZ-2A includes FIR, IIR, and FFT accelerators
- What is the external memory interface of the ADSP-21479BBCZ-2A?
The external memory interface is a 16-bit wide SDR SDRAM interface
- What peripheral interfaces are available on the ADSP-21479BBCZ-2A?
The ADSP-21479BBCZ-2A features a Digital Applications Interface (DAI), S/P DIF Tx/Rx, and an 8-channel asynchronous sample rate converter
- How many PWM channels does the ADSP-21479BBCZ-2A have?
The ADSP-21479BBCZ-2A has 16 Pulse Width Modulation (PWM) channels
- What are the package options for the ADSP-21479BBCZ-2A?
The ADSP-21479BBCZ-2A is available in 196 ball CSP_BGA and 100 lead LQFP packages
- What temperature ranges does the ADSP-21479BBCZ-2A support?
The ADSP-21479BBCZ-2A supports Commercial, Industrial, and Automotive temperature ranges
- Is the ADSP-21479BBCZ-2A compatible with previous SHARC Processors?
Yes, the ADSP-21479BBCZ-2A is pin-compatible and code-compatible with all prior SHARC Processors
- What is the Variable Instruction Set Architecture (VISA) feature?
The Variable Instruction Set Architecture (VISA) allows the code size to be decreased by 20% to 30% and increases the memory size availability
