Overview
The ADSP-21161NCCAZ100, produced by Analog Devices Inc., is a low-cost derivative of the ADSP-21160 and features the Super Harvard Architecture. This 32-bit Digital Signal Processor (DSP) is optimized for high-performance DSP applications. It includes a 100 MHz or 110 MHz core, dual-ported on-chip SRAM, an integrated I/O processor with multiprocessing support, and multiple internal buses to eliminate I/O bottlenecks. The ADSP-21161N is fabricated in a state-of-the-art, high-speed, low-power CMOS process, enabling it to perform 660 million floating-point operations per second with its SIMD computational hardware running at 110 MHz.
Key Specifications
| Specification | Details |
|---|---|
| Core Frequency | 100 MHz or 110 MHz |
| Architecture | Super Harvard Architecture (SHARC) |
| Instruction Cycle Time | 10 ns or 9 ns |
| On-Chip Memory | 1M bit dual-ported SRAM |
| Memory Configuration | Up to 32K words of 32-bit data, 64K words of 16-bit data, or 21K words of 48-bit instructions |
| I/O Processor | Supports 14 DMA channels, four serial ports, two link ports, SDRAM controller, SPI interface, and external parallel bus |
| Package | 225-CSPBGA (17x17) |
| Performance | 660 million floating-point operations per second |
Key Features
- SIMD Architecture: Single-instruction multiple-data architecture with two computational units, doubling cycle performance compared to the ADSP-2106x.
- Integrated I/O Processor: Supports 14 DMA channels, four serial ports, two link ports, SDRAM controller, SPI interface, and external parallel bus.
- Memory and Buses: 1M bit dual-ported SRAM, multiple internal buses for efficient data transfers, and glueless multiprocessing support for up to six ADSP-21161N SHARCs.
- Host Processor Interface: Allows host port read/write of IOP registers and DMA transfers for program downloads.
- Low Power CMOS Process: Fabricated in a state-of-the-art, high-speed, low-power CMOS process.
Applications
- High-Performance DSP Applications: Ideal for applications requiring intensive digital signal processing such as audio processing, image processing, and telecommunications.
- Multiprocessing Systems: Supports glueless multiprocessing for up to six ADSP-21161N SHARCs, making it suitable for complex, multi-processor systems.
- Embedded Systems: Used in various embedded systems that require high computational power and efficient data processing.
Q & A
- What is the core frequency of the ADSP-21161N?
The core frequency of the ADSP-21161N is 100 MHz or 110 MHz.
- What type of architecture does the ADSP-21161N use?
The ADSP-21161N uses the Super Harvard Architecture (SHARC).
- How much on-chip memory does the ADSP-21161N have?
The ADSP-21161N has 1M bit dual-ported SRAM.
- What is the instruction cycle time of the ADSP-21161N?
The instruction cycle time is 10 ns or 9 ns.
- Does the ADSP-21161N support multiprocessing?
Yes, it supports glueless multiprocessing for up to six ADSP-21161N SHARCs.
- What is the package type of the ADSP-21161NCCAZ100?
The package type is 225-CSPBGA (17x17).
- How many floating-point operations per second can the ADSP-21161N perform?
The ADSP-21161N can perform 660 million floating-point operations per second.
- What are some key features of the integrated I/O processor?
The integrated I/O processor supports 14 DMA channels, four serial ports, two link ports, SDRAM controller, SPI interface, and external parallel bus.
- Can the ADSP-21161N be used in embedded systems?
Yes, it is commonly used in various embedded systems that require high computational power and efficient data processing.
- How does the ADSP-21161N handle memory accesses?
The memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words, and each memory block can store combinations of code and data).
