Overview
The ADSP-21062LKB-160 is a high-performance signal processing microcomputer from Analog Devices Inc., part of the SHARC (Super Harvard Architecture Computer) family. This 32-bit processor is optimized for high-performance DSP (Digital Signal Processing) applications, offering advanced capabilities and levels of performance. The ADSP-21062L builds on the ADSP-21000 DSP core, integrating a dual-ported on-chip SRAM and various I/O peripherals supported by a dedicated I/O bus. Fabricated in a high-speed, low-power CMOS process, it operates at 40 MHz with a 25 ns instruction cycle time and achieves 120 MFLOPS peak performance.
Key Specifications
| Specification | Details |
|---|---|
| Processor Core | 40 MHz SISD SHARC Core |
| Instruction Cycle Time | 25 ns |
| Peak Performance | 120 MFLOPS |
| Memory | 2 Mbits of on-chip dual-ported SRAM |
| Math Support | IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math |
| Link Ports | Six Link Ports for point-to-point connectivity and array multiprocessing |
| Serial Ports | Two synchronous serial ports with independent transmit and receive functions |
| DMA Controller | 10 Channel DMA controller |
| Host Processor Interface | Host Processor Interface |
| Operating Voltage | 3.3 V |
| Temperature Range | 0°C to +85°C |
| Package | 225-Ball PBGA (23mm x 20mm) |
Key Features
- High Performance DSP Core: The ADSP-21062L features a high-performance floating-point DSP core, optimized for DSP applications.
- Integrated On-Chip System Features: Includes 2 Mbits of dual-ported SRAM, host processor interface, DMA controller, serial ports, and link ports for glueless DSP multiprocessing.
- Code Compatibility: Code compatible with all SHARC processors, ensuring ease of development and migration.
- Mathematical Capabilities: Supports IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math.
- Efficient Memory Access: Dual-ported memory allows single-cycle, independent accesses by the core processor and I/O processor or DMA controller.
- Scalable Multiprocessing: Glueless connection for scalable DSP multiprocessing using six Link Ports.
Applications
The ADSP-21062L is suited for a variety of high-performance DSP applications, including:
- Audio Processing: Real-time audio processing, audio codecs, and audio effects.
- Image Processing: Image and video processing, including compression and enhancement.
- Industrial Control: High-speed data acquisition and control in industrial environments.
- Medical Devices: Medical imaging, diagnostic equipment, and patient monitoring systems.
- Telecommunications: Baseband processing in wireless and wired communication systems.
Q & A
- What is the peak performance of the ADSP-21062L?
The ADSP-21062L achieves a peak performance of 120 MFLOPS.
- What is the instruction cycle time of the ADSP-21062L?
The instruction cycle time is 25 ns.
- How much on-chip SRAM does the ADSP-21062L have?
The ADSP-21062L has 2 Mbits of on-chip dual-ported SRAM.
- What types of mathematical operations does the ADSP-21062L support?
The ADSP-21062L supports IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math.
- How many Link Ports does the ADSP-21062L have?
The ADSP-21062L has six Link Ports for point-to-point connectivity and array multiprocessing.
- What is the operating voltage of the ADSP-21062L?
The operating voltage is 3.3 V.
- What is the temperature range for the ADSP-21062L?
The temperature range is 0°C to +85°C.
- What package options are available for the ADSP-21062L?
The ADSP-21062L is available in a 225-Ball PBGA (23mm x 20mm) package.
- Is the ADSP-21062L code compatible with other SHARC processors?
Yes, the ADSP-21062L is code compatible with all SHARC processors.
- What is the purpose of the DMA controller in the ADSP-21062L?
The DMA controller manages data transfers between different parts of the system, enhancing overall system performance.
