Overview
The AD9558BCPZ-REEL7, produced by Analog Devices Inc., is a low loop bandwidth clock multiplier designed to provide jitter cleanup and synchronization for various systems, including synchronous optical networks (OTN/SONET/SDH). This device operates over an industrial temperature range of −40°C to +85°C and is packaged in a 9 mm × 9 mm LFCSP (Lead Frame Chip Scale Package).
The AD9558 generates an output clock synchronized to up to four external input references. It features a digital phase-locked loop (PLL) that reduces input time jitter or phase noise associated with the external references. The device also includes digitally controlled loop and holdover circuitry, ensuring continuous generation of a low jitter output clock even when all reference inputs have failed.
Key Specifications
| Parameter | Min | Typ | Max | Unit | Test Conditions/Comments |
|---|---|---|---|---|---|
| Operating Temperature Range | −40 | +85 | °C | Industrial temperature range | |
| Input Voltage High (VIH) | 1.2 | 1.5 | V | Threshold Setting 1.0 V | |
| Input Voltage Low (VIL) | 0.35 | 0.5 | V | Threshold Setting 0.5 V | |
| Input Current (IINH, IINL) | ±60 | ±100 | µA | ||
| Input Capacitance (CIN) | 3 | pF | |||
| Output Frequency Range | 750 | 805 | MHz | VCO range limitations apply | |
| Output High Voltage (VOH) | DVDD3 − 0.4 | V | IOH = 1 mA | ||
| Output Low Voltage (VOL) | 0.4 | V | IOL = 1 mA |
Key Features
- Digital phase-locked loop (PLL) for reducing input time jitter or phase noise.
- Digitally controlled loop and holdover circuitry to ensure continuous low jitter output clock generation even when all reference inputs fail.
- Supports up to four external input references.
- Operates over an industrial temperature range of −40°C to +85°C.
- 9 mm × 9 mm LFCSP package.
- Jitter cleanup and synchronization for SONET/SDH/OTN clocks up to 100 Gbps, including FEC.
- Stratum 3 holdover, jitter cleanup, and phase transient control.
Applications
- Network synchronization, including synchronous Ethernet and SDH to OTN mapping/demapping.
- Cleanup of reference clock jitter.
- SONET/SDH/OTN clocks up to 100 Gbps, including FEC.
- Wireless base station controllers.
- Cable infrastructure.
- Data communications.
Q & A
- What is the operating temperature range of the AD9558?
The AD9558 operates over an industrial temperature range of −40°C to +85°C.
- How many external input references can the AD9558 support?
The AD9558 can support up to four external input references.
- What is the primary function of the digital phase-locked loop (PLL) in the AD9558?
The primary function of the PLL is to reduce input time jitter or phase noise associated with the external references.
- What happens to the output clock if all reference inputs fail?
The digitally controlled loop and holdover circuitry ensure continuous generation of a low jitter output clock even when all reference inputs have failed.
- What are some of the key applications of the AD9558?
The AD9558 is used in network synchronization, reference clock jitter cleanup, SONET/SDH/OTN clocks, wireless base station controllers, cable infrastructure, and data communications.
- What is the package type and size of the AD9558?
The AD9558 is packaged in a 9 mm × 9 mm LFCSP (Lead Frame Chip Scale Package).
- What is the output frequency range of the AD9558?
The output frequency range of the AD9558 is from 750 MHz to 805 MHz, with VCO range limitations applying.
- What are the input voltage high and low thresholds for the AD9558?
The input voltage high (VIH) and low (VIL) thresholds vary based on the voltage setting but typically range from 1.2 V to 1.5 V for VIH and 0.35 V to 0.5 V for VIL.
- What is the input capacitance of the AD9558?
The input capacitance (CIN) of the AD9558 is 3 pF.
- How does the AD9558 handle phase transient control?
The AD9558 includes features for phase transient control as part of its Stratum 3 holdover and jitter cleanup capabilities.
