Overview
The AD9231BCPZRL7-65 is a high-performance, monolithic, dual-channel analog-to-digital converter (ADC) produced by Analog Devices Inc. This 12-bit ADC operates from a single 1.8 V analog power supply and features a separate digital output driver supply that can accommodate 1.8 V to 3.3 V logic families. It is designed for low power consumption and ease of use, making it suitable for a variety of high-speed data acquisition applications.
Key Specifications
| Parameter | Value | Unit |
|---|---|---|
| Resolution | 12 bits | |
| Sampling Rate | 20 MSPS / 40 MSPS / 65 MSPS / 80 MSPS | |
| Analog Supply Voltage | 1.8 V | V |
| Digital Output Supply Voltage | 1.8 V to 3.3 V | V |
| Signal-to-Noise Ratio (SNR) | 71.3 dBFS at 9.7 MHz input, 69.0 dBFS at 200 MHz input | dBFS |
| Spurious Free Dynamic Range (SFDR) | 93 dBc at 9.7 MHz input, 83 dBc at 200 MHz input | dBc |
| Power Consumption | 32 mW per channel at 20 MSPS, 71 mW per channel at 80 MSPS | mW |
| Input Type | Differential | |
| Input Bandwidth | 700 MHz | MHz |
| Operating Temperature Range | -40°C to +85°C | °C |
| Package | 64-Lead LFCSP (9mm x 9mm x 0.75mm) |
Key Features
- High performance sample-and-hold circuit with excellent performance for input frequencies up to 200 MHz
- On-chip voltage reference and sample-and-hold circuit
- Low power consumption: 32 mW per channel at 20 MSPS and 71 mW per channel at 80 MSPS
- Differential input with 700 MHz bandwidth and 2 V p-p differential analog input
- Serial port control options for data output formatting, internal clock divider, power-down, DCO/DATA timing and offset adjustments, and voltage reference modes
- Optional clock duty cycle stabilizer (DCS) to compensate for wide variations in the clock duty cycle
- Integer 1-to-8 input clock divider and data output multiplex option
- Built-in selectable digital test pattern generation including deterministic and pseudorandom patterns
- Energy-saving power-down modes
- Data clock out with programmable clock and data alignment
Applications
- Communications systems
- Diversity radio systems
- Multimode digital receivers
Q & A
- What is the resolution of the AD9231BCPZRL7-65 ADC?
The AD9231BCPZRL7-65 has a 12-bit resolution.
- What are the available sampling rates for the AD9231BCPZRL7-65?
The available sampling rates are 20 MSPS, 40 MSPS, 65 MSPS, and 80 MSPS.
- What is the analog supply voltage for the AD9231BCPZRL7-65?
The analog supply voltage is 1.8 V.
- What is the range of the digital output supply voltage for the AD9231BCPZRL7-65?
The digital output supply voltage can range from 1.8 V to 3.3 V.
- What is the signal-to-noise ratio (SNR) of the AD9231BCPZRL7-65 at different input frequencies?
The SNR is 71.3 dBFS at 9.7 MHz input and 69.0 dBFS at 200 MHz input.
- What is the spurious free dynamic range (SFDR) of the AD9231BCPZRL7-65 at different input frequencies?
The SFDR is 93 dBc at 9.7 MHz input and 83 dBc at 200 MHz input.
- How much power does the AD9231BCPZRL7-65 consume per channel at different sampling rates?
The power consumption is 32 mW per channel at 20 MSPS and 71 mW per channel at 80 MSPS.
- What type of input does the AD9231BCPZRL7-65 support?
The AD9231BCPZRL7-65 supports differential inputs.
- What is the operating temperature range of the AD9231BCPZRL7-65?
The operating temperature range is -40°C to +85°C.
- What is the package type of the AD9231BCPZRL7-65?
The package type is a 64-Lead LFCSP (9mm x 9mm x 0.75mm).
