Overview
The AD808-622BRRL, produced by Analog Devices Inc., is a fiber optic receiver integrated circuit designed to provide comprehensive receiver functions for 622 Mbps NRZ (Non-Return-to-Zero) data. This device is integral in the construction of highly integrated, low-cost, and low-power SONET OC-12 or SDH STM-4 fiber optic receivers. It combines data quantization, signal level detection, clock recovery, and data retiming capabilities, making it a crucial component in high-speed optical communication systems.
Key Specifications
Parameter | Condition | Min | Typ | Max | Units |
---|---|---|---|---|---|
Input Voltage Range | @ PIN or NIN | 2.5 VS | V | V | |
Input Sensitivity, VSENSE | PIN-NIN, BER = ≤ 1 × 10–10 | 10 | 4.0 | mV | |
Input Overdrive, VOD | BER = ≤ 1 × 10–10 | 5 | 2.0 | mV | |
Input Offset Voltage | 1.0 | mV | |||
Input Current | 10 | µA | |||
Input RMS Noise | BER = ≤ 1 × 10–10 | 100 | µV | ||
Upper –3 dB Bandwidth | 600 | 800 | MHz | ||
Input Resistance | 10 kΩ | ||||
Input Capacitance | 2 pF | ||||
Power Supply Voltage | 4.5 | 5.5 | V | ||
Power Supply Current | VCC = 5.0 V, VEE = GND, TA = +25°C | 55 | 80 | 100 mA | |
Operating Temperature | -40°C | +85°C | |||
Package | 16-Lead Narrow SOIC |
Key Features
- Meets CCITT G.958 requirements for STM-4 and Bellcore TR-NWT-000253 requirements for OC-12.
- 622 Mbps clock recovery and data retiming with no preamble required.
- Phase-Locked Loop (PLL) type clock with factory-trimmed VCO center frequency, eliminating the need for external components like crystals or SAW filters.
- Quantizer sensitivity of 4 mV and programmable level detect range from 10 mV to 40 mV.
- Single supply operation at +5 V or ±5 V with low power consumption of 400 mW.
- ECL/PECL compatible output.
- Signal level detect circuit with 3 dB optical hysteresis to prevent chatter.
- High jitter tolerance and low phase drift.
Applications
- SONET OC-12 and SDH STM-4 fiber optic receivers.
- High-speed optical communication systems.
- Telecommunication networks requiring reliable and high-speed data transmission.
- Integrated fiber optic receiver modules.
Q & A
- What is the primary function of the AD808-622BRRL?
The AD808-622BRRL provides receiver functions including data quantization, signal level detection, clock recovery, and data retiming for 622 Mbps NRZ data.
- What are the key standards that the AD808-622BRRL complies with?
The device meets CCITT G.958 requirements for STM-4 and Bellcore TR-NWT-000253 requirements for OC-12.
- What type of clock recovery does the AD808-622BRRL use?
The AD808-622BRRL uses a Phase-Locked Loop (PLL) type clock with a factory-trimmed VCO center frequency.
- What is the input sensitivity of the AD808-622BRRL?
The input sensitivity is 4 mV.
- What is the power supply voltage range for the AD808-622BRRL?
The power supply voltage range is from 4.5 V to 5.5 V.
- What is the typical power consumption of the AD808-622BRRL?
The typical power consumption is 400 mW.
- What type of output is compatible with the AD808-622BRRL?
The output is ECL/PECL compatible.
- What is the operating temperature range of the AD808-622BRRL?
The operating temperature range is from -40°C to +85°C.
- What is the package type of the AD808-622BRRL?
The package type is a 16-Lead Narrow SOIC.
- Does the AD808-622BRRL require an external crystal or SAW filter for clock recovery?
No, the AD808-622BRRL does not require external components like crystals or SAW filters for clock recovery.