Overview
The AD808-622BRZRL7, produced by Analog Devices Inc., is a highly integrated fiber optic receiver designed for high-speed data transmission. This component combines the functions of data quantization, signal level detection, clock recovery, and data retiming, making it an essential part of optical communication systems. It is particularly suited for applications requiring 622 Mbps NRZ (Non-Return-to-Zero) data transmission, such as in STM-4 and OC-12 systems.
Key Specifications
Parameter | Condition | Min | Typ | Max | Units |
---|---|---|---|---|---|
Input Voltage Range @ PIN or NIN | 2.5 VS | V | |||
Input Sensitivity, VSENSE | BER = ≤ 1 × 10–10 | 4.0 mV | mV | ||
Input Overdrive | BER = ≤ 1 × 10–10 | 5 mV | 2.0 mV | mV | |
Input Offset Voltage | 1.0 mV | mV | |||
Input Current | 10 µA | µA | |||
Upper –3 dB Bandwidth | 600 MHz | 800 MHz | MHz | ||
Data Rate | 622 Mbps | Mbps | |||
Max Operating Temperature | °C | ||||
Max Power Dissipation | 400 mW | mW | |||
Max Supply Voltage | +5 V or –5.2 V | V | |||
Output Jitter | 27–1 PRN Sequence | 2.5 Degrees | 3.6 Degrees | rms | |
Phase Drift | 240 Bits, No Transitions | 50 Degrees | Degrees | ||
Number of Pins | 16 |
Key Features
- Meets CCITT G.958 Requirements for STM-4 Regenerator—Type A and Bellcore TR-NWT-000253 Requirements for OC-12.
- Accepts NRZ data without the need for a preamble.
- Phase-Locked Loop (PLL) type clock recovery without requiring an external crystal or SAW filter.
- Single supply operation: +5 V or –5.2 V.
- Low power consumption: 400 mW.
- 10 kH ECL/PECL compatible output.
- Quantizer sensitivity: 4 mV.
- Level detect range: 10 mV to 40 mV, programmable.
- Output jitter: 2.5 degrees RMS.
Applications
The AD808-622BRZRL7 is designed for high-speed optical communication systems, particularly in applications such as:
- STM-4 (622 Mbps) and OC-12 (622 Mbps) systems.
- Fiber optic receivers requiring data quantization, signal level detection, clock recovery, and data retiming.
- Telecommunication networks and optical transmission systems.
Q & A
- What is the primary function of the AD808-622BRZRL7?
The AD808-622BRZRL7 provides the functions of data quantization, signal level detection, clock recovery, and data retiming for 622 Mbps NRZ data. - What are the key standards met by the AD808-622BRZRL7?
The AD808-622BRZRL7 meets CCITT G.958 Requirements for STM-4 Regenerator—Type A and Bellcore TR-NWT-000253 Requirements for OC-12. - Does the AD808-622BRZRL7 require an external crystal for clock recovery?
No, the AD808-622BRZRL7 uses a Phase-Locked Loop (PLL) type clock recovery that does not require an external crystal or SAW filter. - What is the input sensitivity of the AD808-622BRZRL7?
The input sensitivity of the AD808-622BRZRL7 is 4 mV. - What is the maximum power dissipation of the AD808-622BRZRL7?
The maximum power dissipation is 400 mW. - What is the output jitter of the AD808-622BRZRL7?
The output jitter is 2.5 degrees RMS. - What is the phase drift of the AD808-622BRZRL7?
The phase drift is 50 degrees over 240 bits with no transitions. - What is the operating supply voltage range of the AD808-622BRZRL7?
The operating supply voltage range is +5 V or –5.2 V. - How many pins does the AD808-622BRZRL7 have?
The AD808-622BRZRL7 has 16 pins. - What is the upper –3 dB bandwidth of the AD808-622BRZRL7?
The upper –3 dB bandwidth is 600 MHz to 800 MHz.