Overview
The TMS320C6746EZWT4 is a fixed- and floating-point Digital Signal Processor (DSP) from Texas Instruments, part of the C674x DSP family. This device is designed for low-power applications and offers significant performance enhancements compared to other members of the TMS320C6000 platform. It features a 2-level cache-based architecture, with 32KB of L1 program and data caches, and a 256KB unified L2 cache. The DSP core supports both fixed-point and floating-point operations, making it versatile for a wide range of applications.
The TMS320C6746EZWT4 is particularly suited for original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) who need to develop devices with robust operating systems, rich user interfaces, and high processor performance. The device includes a comprehensive set of peripherals and interfaces, facilitating communication and control of external devices.
Key Specifications
| Specification | Details |
|---|---|
| Processor Speed | 375 MHz and 456 MHz versions |
| MIPS and MFLOPS | Up to 3648 MIPS and 2746 MFLOPS |
| Cache Memory | 32KB L1P Program Cache, 32KB L1D Data Cache, 256KB L2 Unified Cache |
| Instruction Set | Superset of C67x+ and C64x+ ISAs, byte-addressable (8-, 16-, 32-, and 64-bit data) |
| Registers | 64 general-purpose registers (32-bit) |
| ALU Functional Units | Six ALU (32- and 40-bit) functional units |
| Floating-Point Support | Supports 32-bit integer, SP (IEEE Single Precision/32-bit), and DP (IEEE Double Precision/64-bit) floating point |
| Memory Interfaces | EMIFA, DDR2/Mobile DDR controller, 16-bit SDRAM, NOR, NAND |
| Peripheral Interfaces | UART, SPI, I2C, MMC/SD, USB 2.0 OTG, EMAC, VPIF, uPP |
| Package | NFBGA (361 pins), 16.00 mm x 16.00 mm |
Key Features
- C674x DSP Core: Load-store architecture with nonaligned support, six ALU functional units, and support for 32-bit integer and IEEE floating-point operations.
- Cache Architecture: 32KB L1P and L1D caches, 256KB unified L2 cache.
- EDMA3 Controller: 64 independent DMA channels, 16 quick DMA channels, programmable transfer burst size.
- Peripheral Set: Includes UART, SPI, I2C, MMC/SD, USB 2.0 OTG, EMAC, VPIF, uPP, and more.
- Programmable Real-Time Unit Subsystem (PRUSS): Two independent PRU cores with 32-bit load-store RISC architecture.
- Power Management: Standard power-management mechanism, clock gating, and entire subsystem under a single PSC clock gating domain.
- Audio and Video Interfaces: McASP, McBSP, and VPIF for various audio and video formats.
- Networking: 10/100 Mbps Ethernet MAC (EMAC) with MII and RMII interfaces.
Applications
- Currency Inspection: Utilizes the DSP's advanced signal processing capabilities for image and signal analysis.
- Biometric Identification: Leverages the DSP's performance for complex biometric algorithms such as fingerprint or facial recognition.
- Machine Vision (Low-End): Suitable for low-end machine vision applications requiring real-time image processing and analysis.
- General Embedded Systems: Ideal for various embedded systems requiring high-performance signal processing and low power consumption.
Q & A
- What is the maximum clock speed of the TMS320C6746EZWT4?
The maximum clock speed is 456 MHz.
- What type of cache architecture does the TMS320C6746EZWT4 use?
The device uses a 2-level cache architecture with 32KB L1P and L1D caches and a 256KB unified L2 cache.
- What is the EDMA3 controller capable of?
The EDMA3 controller has 64 independent DMA channels, 16 quick DMA channels, and programmable transfer burst size.
- Does the TMS320C6746EZWT4 support floating-point operations?
Yes, it supports 32-bit integer, SP (IEEE Single Precision/32-bit), and DP (IEEE Double Precision/64-bit) floating-point operations.
- What types of memory interfaces are available on the TMS320C6746EZWT4?
The device includes EMIFA, DDR2/Mobile DDR controller, 16-bit SDRAM, NOR, and NAND memory interfaces.
- What peripheral interfaces are supported by the TMS320C6746EZWT4?
The device supports UART, SPI, I2C, MMC/SD, USB 2.0 OTG, EMAC, VPIF, and uPP interfaces.
- What is the purpose of the Programmable Real-Time Unit Subsystem (PRUSS)?
The PRUSS includes two independent PRU cores with 32-bit load-store RISC architecture for real-time processing tasks.
- How does the TMS320C6746EZWT4 manage power consumption?
The device features a standard power-management mechanism, clock gating, and an entire subsystem under a single PSC clock gating domain.
- What are some common applications of the TMS320C6746EZWT4?
Common applications include currency inspection, biometric identification, machine vision, and general embedded systems requiring high-performance signal processing.
- What development tools are available for the TMS320C6746EZWT4?
The device is supported by C compilers, a DSP assembly optimizer, and a Windows debugger interface.
