Overview
The TMS320C6746BZWT3 is a fixed- and floating-point digital signal processor (DSP) from Texas Instruments, based on the C674x DSP core. This low-power applications processor is designed to provide high performance with significantly lower power consumption compared to other members of the TMS320C6000 platform. It is ideal for original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to develop devices with robust operating systems, rich user interfaces, and high processor performance.
The device features a 2-level cache architecture, enhanced direct memory access controller (EDMA3), and a wide range of peripherals, making it versatile for various applications. It also includes software support such as TI DSP BIOS, Chip Support Library, and DSP Library, along with comprehensive development tools.
Key Specifications
| Specification | Details |
|---|---|
| Processor Core | 375- and 456-MHz C674x Fixed- and Floating-Point VLIW DSP |
| Instruction Set | Superset of C67x+ and C64x+ ISAs, up to 3648 MIPS and 2746 MFLOPS |
| Cache Memory | 32KB L1P Program RAM/Cache, 32KB L1D Data RAM/Cache, 256KB L2 Unified Mapped RAM/Cache |
| EDMA3 | 64 independent channels, 16 QDMA channels, 2 channel controllers, 3 transfer controllers |
| Floating-Point Support | Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit), and DP (IEEE Double Precision/64-Bit) Floating Point |
| Memory Interfaces | DDR2/Mobile DDR controller, EMIFA for asynchronous and SDRAM, NOR, NAND flash |
| UART Modules | Three configurable 16550-Type UART modules with modem control signals and 16-Byte FIFO |
| SPI and MMC/SD Interfaces | Two SPIs with multiple chip selects, two MMC/SD card interfaces with SDIO |
| I2C Bus | Two Master and Slave Inter-Integrated Circuits (I2C Bus) |
| Host-Port Interface | One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address and Data Bus |
| Video Port Interface | Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video Capture Channels |
| Package | NFBGA (361) package, 16.00 mm x 16.00 mm body size |
Key Features
- C674x Instruction Set Features: Superset of the C67x+ and C64x+ ISAs, up to 3648 MIPS and 2746 MFLOPS, byte-addressable (8-, 16-, 32-, and 64-Bit Data), 8-Bit overflow protection, bit-field extract, set, clear, normalization, saturation, bit-counting, compact 16-Bit instructions.
- C674x Two-Level Cache Memory Architecture: 32KB of L1P Program RAM/Cache, 32KB of L1D Data RAM/Cache, 256KB of L2 Unified Mapped RAM/Cache.
- Enhanced Direct Memory Access Controller 3 (EDMA3): 64 independent channels, 16 QDMA channels, 2 channel controllers, 3 transfer controllers.
- Floating-Point VLIW DSP Core: Load-Store Architecture With Nonaligned Support, 64 General-Purpose Registers (32-Bit), Six ALU (32- and 40-Bit) Functional Units.
- Programmable Real-Time Unit Subsystem (PRUSS): Two Independent Programmable Real-Time Unit (PRU) Cores, 32-Bit Load-Store RISC Architecture, 4KB of Instruction RAM Per Core, 512 Bytes of Data RAM Per Core.
- USB 2.0 OTG Port: Integrated PHY, USB 2.0 High- and Full-Speed Client, USB 2.0 High-, Full-, and Low-Speed Host.
- Multichannel Audio Serial Port (McASP): Two Clock Zones and 16 Serial Data Pins, Supports TDM, I2S, and Similar Formats.
- 10/100 Mbps Ethernet MAC (EMAC): IEEE 802.3 Compliant, MII Media-Independent Interface, RMII Reduced Media-Independent Interface.
Applications
- Currency Inspection: The TMS320C6746 can be used in currency inspection systems due to its high processing capabilities and low power consumption.
- Biometric Identification: Suitable for biometric identification applications such as fingerprint or facial recognition due to its robust processing power.
- Machine Vision (Low-End): Ideal for low-end machine vision applications requiring real-time processing and analysis of video data.
Q & A
- What is the core frequency of the TMS320C6746 DSP?
The TMS320C6746 DSP operates at frequencies of 375 MHz and 456 MHz.
- What type of cache memory does the TMS320C6746 have?
The device features a two-level cache architecture with 32KB L1P Program RAM/Cache, 32KB L1D Data RAM/Cache, and 256KB L2 Unified Mapped RAM/Cache.
- What is the EDMA3 controller capable of?
The EDMA3 controller has 64 independent channels, 16 QDMA channels, 2 channel controllers, and 3 transfer controllers.
- Does the TMS320C6746 support floating-point operations?
Yes, it supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit), and DP (IEEE Double Precision/64-Bit) Floating Point operations.
- What types of memory interfaces are available on the TMS320C6746?
The device includes DDR2/Mobile DDR controller, EMIFA for asynchronous and SDRAM, NOR, NAND flash.
- How many UART modules does the TMS320C6746 have?
It has three configurable 16550-Type UART modules with modem control signals and 16-Byte FIFO.
- What is the purpose of the Programmable Real-Time Unit Subsystem (PRUSS)?
The PRUSS includes two independent programmable real-time unit (PRU) cores, each with a 32-Bit Load-Store RISC Architecture, for real-time processing tasks.
- Does the TMS320C6746 support USB and Ethernet?
Yes, it includes a USB 2.0 OTG port and a 10/100 Mbps Ethernet MAC (EMAC).
- What are some common applications of the TMS320C6746?
Common applications include currency inspection, biometric identification, and low-end machine vision.
- What development tools are available for the TMS320C6746?
The device is supported by C compilers, a DSP assembly optimizer, and a Windows debugger interface.
