Overview
The TMS320C6743BZKB3 is a low-power digital signal processor (DSP) from Texas Instruments, based on the TMS320C674x DSP core. This device is designed to offer high processing performance while consuming significantly lower power compared to other members of the TMS320C6000 platform. It is particularly suited for original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly develop and market high-performance devices.
The C6743 DSP core utilizes a two-level cache-based architecture, featuring a 32-KB Level 1 program cache (L1P) and a 32-KB Level 1 data cache (L1D), along with a 128-KB Level 2 cache that can be configured as mapped memory, cache, or a combination of both.
Key Specifications
| Specification | Details |
|---|---|
| Processor Core | 375-MHz TMS320C674x Fixed- and Floating-Point VLIW DSP Core |
| Architecture | Load-Store Architecture with Nonaligned Support |
| Registers | 64 General-Purpose Registers (32-Bit) |
| ALU Functional Units | Six ALU (32- and 40-Bit) Functional Units |
| Floating Point Support | Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit), and DP (IEEE Double Precision/64-Bit) Floating Point |
| Multiply Functional Units | Two Multiply Functional Units |
| Fixed-Point Multiply | Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle |
| Caches | 32-KB L1P, 32-KB L1D, 128-KB L2 Cache |
| External Memory Interfaces | Asynchronous EMIFA and higher speed EMIFB for SDRAM |
| Ethernet MAC | 10/100 Mbps EMAC with MDIO module |
| GPIO | Up to 8 banks of 16 pins of GPIO with programmable interrupt/event generation modes |
| Timers | Two 64-bit general-purpose timers each configurable (one configurable as watchdog) |
| UART Interfaces | Two UART interfaces (one with RTS and CTS) |
| Pulse Width Modulators | Three enhanced high-resolution pulse width modulator (eHRPWM) peripherals |
| Capture and Quadrature Encoded Pulse Peripherals | Three 32-bit enhanced capture (eCAP) and two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals |
Key Features
- Dedicated 16-Bit Time-Base Counter: With period and frequency control.
- Peripheral Set: Includes 10/100 Mbps Ethernet MAC (EMAC) with MDIO module, two I2C Bus interfaces, two multichannel audio serial ports (McASPs), two 64-bit general-purpose timers, up to 8 banks of 16 pins of GPIO, two UART interfaces, three enhanced high-resolution pulse width modulator (eHRPWM) peripherals, three 32-bit enhanced capture (eCAP) module peripherals, and two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals.
- Cache Architecture: Two-level cache-based architecture with 32-KB L1P and L1D caches and a 128-KB L2 cache.
- Mixed-Precision IEEE Floating Point Multiply: Supports various mixed-precision operations such as 2 SP x SP -> SP per clock, 2 SP x SP -> DP every two clocks, etc.
- Instruction Packing and Conditional Instructions: Reduces code size and all instructions are conditional.
- Hardware Support for Modulo Loop and EDMA3: Enhances performance and efficiency.
Applications
- Networking: Utilizes the 10/100 Mbps Ethernet MAC for efficient network communication.
- High-Speed Encoding: Suitable for high-speed data processing and encoding tasks.
- Professional Audio: Supports multichannel audio serial ports and is ideal for professional audio applications.
- Industrial and Automotive Systems: Can be used in various industrial and automotive applications due to its robust peripheral set and low power consumption.
Q & A
- What is the core frequency of the TMS320C6743BZKB3?
The core frequency of the TMS320C6743BZKB3 is up to 375 MHz.
- What type of cache architecture does the TMS320C6743BZKB3 use?
The device uses a two-level cache-based architecture with 32-KB L1P and L1D caches and a 128-KB L2 cache.
- What are the key features of the peripheral set in the TMS320C6743BZKB3?
The peripheral set includes a 10/100 Mbps Ethernet MAC, two I2C Bus interfaces, two multichannel audio serial ports, two 64-bit general-purpose timers, up to 8 banks of GPIO, two UART interfaces, and various pulse width modulator and capture peripherals.
- Does the TMS320C6743BZKB3 support floating-point operations?
Yes, it supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit), and DP (IEEE Double Precision/64-Bit) Floating Point operations.
- What are the external memory interfaces available on the TMS320C6743BZKB3?
The device features an asynchronous EMIFA for slower memories or peripherals and a higher speed EMIFB for SDRAM.
- How many GPIO pins are available on the TMS320C6743BZKB3?
Up to 8 banks of 16 pins of GPIO are available, with programmable interrupt/event generation modes.
- What is the purpose of the EMAC in the TMS320C6743BZKB3?
The EMAC provides an efficient interface between the device and the network, supporting both 10Base-T and 100Base-TX in either half- or full-duplex mode.
- Can the TMS320C6743BZKB3 be used in professional audio applications?
Yes, it is suitable for professional audio applications due to its support for multichannel audio serial ports and other relevant peripherals.
- What software support is available for the TMS320C6743BZKB3?
The device is supported by TI DSP/BIOS, Chip Support Library, and DSP Library.
- Are there any specific precautions for ESD robustness in the TMS320C6743BZKB3?
Yes, it is recommended to avoid using the internal oscillator as a clock source due to susceptibility to radiated noise during ESD strikes. An external 3.3V clock source is recommended instead.
