Overview
The TMS320C6678CYP25 is a Multicore Fixed and Floating Point Digital Signal Processor (DSP) developed by Texas Instruments. It is based on TI's KeyStone multicore architecture and features eight TMS320C66x DSP Core Subsystems, each operating at frequencies of 1.0 to 1.25 GHz, collectively enabling up to 10 GHz of processing power. This device is designed to support high-performance signal processing applications, including mission-critical systems, medical imaging, test and measurement, and automation. The C6678 platform is known for its power efficiency and ease of use, and it maintains backward compatibility with all existing C6000 family of fixed and floating point DSPs.
Key Specifications
| Specification | Details |
|---|---|
| Package | FCBGA (CYP), 841 pins |
| Operating Temperature Range | 0 to 85°C |
| Core Frequency | 1.00 GHz to 1.25 GHz per core |
| Performance | 320 GMAC/160 GFLOP @ 1.25 GHz |
| Memory per Core | 32KB L1P, 32KB L1D, 512KB L2 |
| Shared Memory | 4MB Shared L2 |
| Memory Interface | 64-Bit DDR3 Interface (DDR3-1600), 16-Bit EMIF |
| Networking and Interfaces | Four lanes of SRIO 2.1, Two lanes PCIe Gen2, HyperLink, Ethernet MAC Subsystem |
| Other Interfaces | UART, I2C, SPI, 16 GPIO Pins, Two Telecom Serial Ports (TSIP) |
| Timers and PLLs | Sixteen 64-Bit Timers, Three On-Chip PLLs |
Key Features
- Eight TMS320C66x DSP Core Subsystems at 1.00 GHz and 1.25 GHz
- High performance: 320 GMAC/160 GFLOP @ 1.25 GHz
- Memory: 32KB L1P, 32KB L1D, 512KB L2 per core, 4MB Shared L2
- Multicore Navigator and TeraNet Switch Fabric - 2 Tb
- Network Coprocessors: Packet Accelerator, Security Accelerator
- Four lanes of SRIO 2.1 - 5 Gbaud Per Lane Full Duplex
- Two lanes PCIe Gen2 - 5 Gbaud Per Lane Full Duplex
- HyperLink - 50Gbaud Operation, Full Duplex
- Ethernet MAC Subsystem - Two SGMII Ports w/ 10/100/1000 Mbps operation
- 64-Bit DDR3 Interface (DDR3-1600) - 8 GByte Addressable Memory Space
- 16-Bit EMIF - Async SRAM, NAND and NOR Flash Support
- Two Telecom Serial Ports (TSIP) - 2/4/8 Lanes at 32.768/16.384/8.192
- UART, I2C, SPI interfaces
- 16 GPIO Pins
- Sixteen 64-Bit Timers
- Three On-Chip PLLs
Applications
The TMS320C6678CYP25 is designed to support a variety of high-performance signal processing applications, including:
- Mission-critical systems
- Medical imaging
- Test and measurement
- Automation
Q & A
- What is the core frequency of the TMS320C6678CYP25?
The core frequency of the TMS320C6678CYP25 is 1.00 GHz to 1.25 GHz per core.
- How many DSP cores does the TMS320C6678CYP25 have?
The TMS320C6678CYP25 has eight TMS320C66x DSP Core Subsystems.
- What is the performance of the TMS320C6678CYP25 in terms of GMAC and GFLOP?
The performance is 320 GMAC/160 GFLOP @ 1.25 GHz.
- What type of memory interface does the TMS320C6678CYP25 support?
The device supports a 64-Bit DDR3 Interface (DDR3-1600) and a 16-Bit EMIF for Async SRAM, NAND, and NOR Flash.
- What networking interfaces are available on the TMS320C6678CYP25?
The device includes four lanes of SRIO 2.1, two lanes PCIe Gen2, HyperLink, and an Ethernet MAC Subsystem with two SGMII ports.
- Does the TMS320C6678CYP25 support any serial interfaces?
Yes, it supports UART, I2C, SPI, and two Telecom Serial Ports (TSIP).
- How many GPIO pins does the TMS320C6678CYP25 have?
The device has 16 GPIO pins.
- What is the operating temperature range of the TMS320C6678CYP25?
The operating temperature range is 0 to 85°C.
- Is the TMS320C6678CYP25 backward compatible with other C6000 family DSPs?
Yes, the C66x CorePac DSP is fully backward compatible with all existing C6000 family of fixed and floating point DSPs.
- What is the package type and pin count of the TMS320C6678CYP25?
The package type is FCBGA (CYP) with 841 pins.
