Overview
The SN65LVDS95DGGREP is a Low-Voltage Differential Signaling (LVDS) serializer/deserializer (serdes) transmitter produced by Texas Instruments. This device is designed for high-speed data transmission and is particularly suited for point-to-point subsystem communication with very low Electromagnetic Interference (EMI). The SN65LVDS95DGGREP operates from a single 3.3-V supply, consumes approximately 250 mW, and is packaged in a Thin Shrink Small-Outline Package (TSSOP) with 48 pins.
The device contains three 7-bit parallel-load serial-out shift registers, a 7× clock synthesizer, and four LVDS line drivers. It synchronously transmits 21 bits of single-ended LVTTL (Low-Voltage Transistor-Transistor Logic) data over four balanced-pair conductors, making it ideal for applications requiring high-speed data transfer over short to medium distances.
Key Specifications
| Parameter | Min | Typ | Max | Unit |
|---|---|---|---|---|
| Supply Voltage (VCC) | 3 | 3.3 | 3.6 | V |
| Operating Temperature (TA) | -40 | 85 | °C | |
| High-Level Input Voltage (VIH) | 2 | V | ||
| Low-Level Input Voltage (VIL) | 0.8 | V | ||
| Differential Load Impedance (ZL) | 90 | 132 | Ω | |
| Input Clock Period (tc) | 14.7 | 50 | ns | |
| Quiescent Current (ICC(AVG)) | 85 | 110 | mA | |
| Power Dissipation | 1.316 | W |
Key Features
- Operates from a single 3.3-V supply with low power consumption (approximately 250 mW).
- No external components required for PLL (Phase-Locked Loop).
- Supports data transmission at up to 1.36 Gigabits per second throughput.
- Contains three 7-bit parallel-load serial-out shift registers and four LVDS line drivers.
- Inputs meet or exceed the requirements of ANSI EIA/TIA-644 standard.
- Industrial temperature qualified: -40°C to 85°C.
- 5-V tolerant data inputs.
- Bus pins tolerate 6-kV HBM (Human Body Model) ESD (Electrostatic Discharge).
- Consumes less than 1 mW when disabled.
- Wide phase-lock input frequency range: 20 MHz to 68 MHz.
Applications
- Point-to-point subsystem communication.
- High-speed data transmission over short to medium distances.
- Backplane bus interfaces.
- Virtual backplane transceivers.
- 16-bit bus extensions with parity.
- Industrial and automotive applications requiring high-speed, low-EMI data transmission.
Q & A
- What is the primary function of the SN65LVDS95DGGREP?
The primary function of the SN65LVDS95DGGREP is to serialize 21 bits of single-ended LVTTL data into four LVDS serial streams for high-speed data transmission.
- What is the operating voltage range of the SN65LVDS95DGGREP?
The operating voltage range is from 3 V to 3.6 V.
- What is the temperature range for the SN65LVDS95DGGREP?
The device is industrial temperature qualified, operating from -40°C to 85°C.
- Does the SN65LVDS95DGGREP require external components for the PLL?
No, the SN65LVDS95DGGREP does not require external components for the PLL.
- What is the maximum data throughput of the SN65LVDS95DGGREP?
The maximum data throughput is up to 1.36 Gigabits per second.
- How many LVDS line drivers does the SN65LVDS95DGGREP contain?
The device contains four LVDS line drivers.
- What standard do the inputs of the SN65LVDS95DGGREP meet or exceed?
The inputs meet or exceed the requirements of the ANSI EIA/TIA-644 standard.
- What is the power consumption of the SN65LVDS95DGGREP when disabled?
The device consumes less than 1 mW when disabled.
- What is the phase-lock input frequency range of the SN65LVDS95DGGREP?
The phase-lock input frequency range is from 20 MHz to 68 MHz.
- What type of package is the SN65LVDS95DGGREP available in?
The device is packaged in a Thin Shrink Small-Outline Package (TSSOP) with 48 pins.
