Overview
The SN65LVDS93DGGRG4 is a Low-Voltage Differential Signaling (LVDS) serializer/deserializer (serdes) transmitter produced by Texas Instruments. This integrated circuit is designed to efficiently transmit large amounts of data over short distances with minimal electromagnetic interference (EMI). The SN65LVDS93 contains four 7-bit parallel-load serial-out shift registers, a 7× clock synthesizer, and five LVDS drivers, enabling the synchronous transmission of 28 bits of single-ended LVTTL data over five balanced-pair conductors. This device is particularly suited for point-to-point subsystem communication and is compatible with receivers such as the SN65LVDS94.
Key Specifications
| Specification | Value |
|---|---|
| Data Rate | 1.904 Gbps |
| Function | Serializer |
| Input Type | LVTTL |
| Number of Inputs | 28 |
| Number of Outputs | 4 |
| Output Type | LVDS |
| Operating Temperature | -40°C to 85°C (TA) |
| Mounting Type | Surface Mount |
| Package | 56-TFSOP (0.240", 6.10mm Width) |
| Supplier Device Package | 56-TSSOP |
| Voltage - Supply | 3V ~ 3.6V |
Key Features
- 28:4 Data Channel Compression at up to 1.904 Gigabits per Second Throughput
- Suited for Point-to-Point Subsystem Communication With Very Low EMI
- 28 Data Channels Plus Clock in Low-Voltage TTL and 4 Data Channels Plus Clock Out Low-Voltage Differential
- Selectable Rising or Falling Clock Edge Triggered Inputs
- Bus Pins Tolerate 6-kV HBM ESD
- Operates From a Single 3.3-V Supply and 250 mW (Typ)
- 5-V Tolerant Data Inputs
- Packaged in Thin Shrink Small-Outline Package With 20 Mil Terminal Pitch
- Consumes <1 mW When Disabled
- Wide Phase-Lock Input Frequency Range 20 MHz to 68 MHz
- No External Components Required for PLL
- Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
- Industrial Temperature Qualified: -40°C to 85°C
Applications
- Relay Driver
- Digital Clock, Thermometer, Counter, Voltmeter
- Instrumentation Readouts
- Test Equipment
- Hand Held Instruments
- Bargraph Displays
- Numeric and Non-Numeric Panel Displays
- High and Low Temperature Environments where LCD Display Integrity is Compromised
Q & A
- What is the primary function of the SN65LVDS93DGGRG4?
The primary function of the SN65LVDS93DGGRG4 is to act as a serializer/deserializer (serdes) transmitter, converting 28 bits of single-ended LVTTL data into four serial streams of LVDS data.
- What is the data rate of the SN65LVDS93DGGRG4?
The data rate of the SN65LVDS93DGGRG4 is up to 1.904 Gbps.
- What is the operating temperature range of the SN65LVDS93DGGRG4?
The operating temperature range of the SN65LVDS93DGGRG4 is -40°C to 85°C.
- What type of package does the SN65LVDS93DGGRG4 come in?
The SN65LVDS93DGGRG4 comes in a 56-TFSOP (0.240", 6.10mm Width) package.
- Does the SN65LVDS93DGGRG4 require external components for PLL operation?
No, the SN65LVDS93DGGRG4 does not require external components for PLL operation.
- How does the SN65LVDS93DGGRG4 handle EMI?
The SN65LVDS93DGGRG4 is designed for point-to-point subsystem communication with very low EMI.
- What is the power consumption of the SN65LVDS93DGGRG4 when disabled?
The SN65LVDS93DGGRG4 consumes less than 1 mW when disabled.
- What is the input clock frequency range for the SN65LVDS93DGGRG4?
The input clock frequency range for the SN65LVDS93DGGRG4 is 20 MHz to 68 MHz.
- Is the SN65LVDS93DGGRG4 compatible with other standards?
Yes, the outputs of the SN65LVDS93DGGRG4 meet or exceed the requirements of the ANSI EIA/TIA-644 standard.
- How does the SN65LVDS93DGGRG4 handle clock edge selection?
The SN65LVDS93DGGRG4 allows selectable rising or falling clock edge triggered inputs via the CLKSEL pin.
- What is the purpose of the SHTDN pin on the SN65LVDS93DGGRG4?
The SHTDN pin is an active-low input that inhibits the clock and shuts off the LVDS output drivers for lower power consumption and clears all internal registers at a low level.
