Overview
The SN65LVDS93A-Q1, produced by Texas Instruments, is a FlatLink™ transmitter designed for high-speed data transmission over Low-Voltage Differential Signaling (LVDS) lines. This integrated circuit is optimized for applications requiring the transmission of video data from a graphics processor to a display panel. It supports up to 28 bits of single-ended LVTTL data, which are synchronously transmitted over five balanced-pair conductors. The device operates from a single 3.3-V supply and is compatible with various display resolutions, including HVGA up to HD, with low EMI.
Key Specifications
| Parameter | Min | Typical | Max | Unit |
|---|---|---|---|---|
| Supply Voltage Range (VCC, IOVCC, LVDSVCC, PLLVCC) | -0.5 | - | 4 | V |
| Input Voltage Range | -0.5 | - | IOVCC + 0.5 | V |
| Operating Temperature Range | -40 | - | 85 | °C |
| Transfer Rate | - | - | 135 Mpps | Mega Pixel Per Second |
| Pixel Clock Frequency Range | 10 MHz | - | 135 MHz | Hz |
| Differential Steady-State Output Voltage Magnitude | 250 mV | 350 mV | 450 mV | mV |
| Power Consumption at 75 MHz | - | 170 mW | - | mW |
| Package Type | - | - | TSSOP (56) | - |
| Body Size | - | - | 14.00 mm x 6.10 mm | mm |
Key Features
- LVDS Output Drivers: The device includes five Low-Voltage Differential Signaling (LVDS) line drivers for high-speed data transmission.
- Input Data Tolerance: Supports 1.8 V to 3.3 V tolerant data inputs, allowing direct connection to low-power, low-voltage applications and graphic processors.
- Selectable Clock Edge: Data transmission can be triggered by either the rising or falling edge of the input clock, selectable via the CLKSEL pin.
- Low Power Mode: The device can be put into a low-power consumption mode by asserting the active-low SHTDN input, which inhibits the clock and shuts off the LVDS output drivers.
- Spread Spectrum Clocking (SSC): Supports SSC to reduce EMI.
- Compatibility: Compatible with OMAP™2x, OMAP™3x, and DaVinci™ application processors.
Applications
- LCD Display Panel Driver: Ideal for driving display panels with integrated LVDS receivers.
- UMPC and Netbook PC: Suitable for ultra-mobile PCs and netbooks.
- Digital Picture Frame: Used in digital picture frames and other display-centric devices.
Q & A
- What is the primary function of the SN65LVDS93A-Q1?
The primary function of the SN65LVDS93A-Q1 is to transmit video data from a graphics processor to a display panel using Low-Voltage Differential Signaling (LVDS).
- What is the operating voltage range of the SN65LVDS93A-Q1?
The device operates from a single 3.3-V supply, and the input data is tolerant from 1.8 V to 3.3 V.
- What is the maximum transfer rate of the SN65LVDS93A-Q1?
The maximum transfer rate is up to 135 Mpps (Mega Pixel Per Second).
- How can the clock edge be selected for data transmission?
The clock edge can be selected by inputting a high level to CLKSEL for a rising edge or a low level for a falling edge.
- What is the purpose of the SHTDN input?
The SHTDN input is used to put the device into low-power mode by asserting it low, which inhibits the clock and shuts off the LVDS output drivers.
- What are the compatible processors with the SN65LVDS93A-Q1?
The device is compatible with OMAP™2x, OMAP™3x, and DaVinci™ application processors.
- What is the recommended package type for the SN65LVDS93A-Q1?
The recommended package type is TSSOP (56).
- What is the typical power consumption at 75 MHz?
The typical power consumption at 75 MHz is 170 mW.
- Does the SN65LVDS93A-Q1 support Spread Spectrum Clocking (SSC)?
Yes, the device supports SSC to reduce EMI.
- What are some common applications of the SN65LVDS93A-Q1?
Common applications include LCD display panel drivers, UMPC and netbook PCs, and digital picture frames.
- What is the recommended PCB design for the SN65LVDS93A-Q1?
It is recommended to keep one common GND layer underneath the device and connect all ground terminals directly to this plane.
