Overview
The SCANSTA112SM from Texas Instruments is a 7-port multidrop IEEE 1149.1 (JTAG) multiplexer designed to extend the IEEE Std. 1149.1 test bus into a multidrop test bus environment. This device enhances test throughput and allows for the removal of a board from the system while retaining test access to the remaining modules. It supports up to 7 local IEEE 1149.1 scan chains, which can be accessed individually or combined serially, making it ideal for complex system testing and programming.
Key Specifications
| Specification | Description |
|---|---|
| Package Type | FBGA-100 (10x10) |
| VCC Supply Operation | 3.0-3.6V |
| Address Inputs | 8 address inputs supporting up to 249 unique slot addresses, an interrogation address, broadcast address, and 4 multi-cast group addresses |
| Local Scan Ports | 7 IEEE 1149.1-compatible configurable local scan ports |
| Backplane and LSP0 Ports | Bi-directional, interchangeable master or slave ports |
| TCK Counter | 32-bit TCK counter for built-in self-test operations |
| LFSR Signature Compactor | 16-bit LFSR signature compactor |
| TRST | TRST on all local scan ports, capable of ignoring TRST of the backplane port when it becomes the slave |
| Mode Register | Allows local TAPs to be bypassed, selected for insertion into the scan chain individually, or serially in groups of two or three |
| Transparent Mode | Can be enabled with a single instruction to buffer the backplane IEEE 1149.1 pins to those on a single local scan port |
| Live Insertion/Withdrawal | Supports live insertion/withdrawal |
Key Features
- True IEEE 1149.1 Hierarchical and Multidrop Addressable Capability: Extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment.
- Addressing Scheme: Supports up to 249 unique slot addresses, an interrogation address, broadcast address, and 4 multi-cast group addresses.
- Bi-directional Backplane and LSP0 Ports: These ports are interchangeable and can act as master or slave ports.
- Stitcher Mode: Bypasses Level 1 and 2 protocols for efficient testing.
- Mode Register: Allows local TAPs to be bypassed, selected for insertion into the scan chain individually, or serially in groups of two or three.
- Transparent Mode: Can be enabled with a single instruction to conveniently buffer the backplane IEEE 1149.1 pins to those on a single local scan port.
- General Purpose Local Port Pass Through Bits: Useful for delivering write pulses for flash programming or monitoring device status.
- Known Power-Up State and TRST: Ensures predictable behavior and control over local scan ports.
- 32-bit TCK Counter and 16-bit LFSR Signature Compactor: Enables built-in self-test operations and signature compaction.
Applications
- Board-Level Testing: Ideal for managing multiple scan chains on a single board, improving fault isolation, and reducing test times.
- System-Level Testing: Supports hierarchical and multidrop configurations, allowing for system-wide structural testing and programming.
- Backplane and Inter-Board Testing: Facilitates testing across multiple boards by parking local TAP controllers in stable states via a park instruction.
- Flash Programming and Device Monitoring: General purpose local port pass through bits are useful for delivering write pulses for flash programming or monitoring device status.
Q & A
- What is the primary function of the SCANSTA112SM?
The primary function of the SCANSTA112SM is to extend the IEEE Std. 1149.1 test bus into a multidrop test bus environment, supporting up to 7 local IEEE 1149.1 scan chains.
- How does the addressing scheme work in the SCANSTA112SM?
The addressing scheme supports up to 249 unique slot addresses, an interrogation address, broadcast address, and 4 multi-cast group addresses by loading the instruction register with a value matching that of the slot inputs.
- What is the significance of the bi-directional backplane and LSP0 ports?
The bi-directional backplane and LSP0 ports are interchangeable and can act as master or slave ports, allowing an alternate test master to take control of the entire scan chain network.
- How does the stitcher mode function in the SCANSTA112SM?
The stitcher mode bypasses Level 1 and 2 protocols, enabling efficient testing by allowing self-test operations to be performed on one port while other scan chains are simultaneously tested.
- What is the purpose of the mode register in the SCANSTA112SM?
The mode register allows local TAPs to be bypassed, selected for insertion into the scan chain individually, or serially in groups of two or three.
- How does the transparent mode work in the SCANSTA112SM?
The transparent mode can be enabled with a single instruction to conveniently buffer the backplane IEEE 1149.1 pins to those on a single local scan port.
- What is the role of the 32-bit TCK counter in the SCANSTA112SM?
The 32-bit TCK counter enables built-in self-test operations to be performed on one port while other scan chains are simultaneously tested.
- Can the SCANSTA112SM support live insertion/withdrawal?
Yes, the SCANSTA112SM supports live insertion/withdrawal, allowing for dynamic changes in the system without disrupting test access.
- How does the SCANSTA112SM facilitate system-level testing?
The SCANSTA112SM facilitates system-level testing by supporting hierarchical and multidrop configurations, allowing a test controller to dynamically select specific portions of the network for participation in scan operations.
- What are the general purpose local port pass through bits used for in the SCANSTA112SM?
The general purpose local port pass through bits are useful for delivering write pulses for flash programming or monitoring device status.
