Overview
The LMK04828SNKDTEP, produced by Texas Instruments, is an ultra-low-noise clock jitter cleaner that supports the JESD204B standard. This device is renowned for its high performance and is designed to provide flexible and high-performance clocking trees. It features a dual PLL architecture, known as PLLatinum™, which includes two integrated low-noise VCOs and a phase detector rate up to 155 MHz. The device is particularly suited for applications requiring precise clock synchronization and low jitter, such as in high-speed data conversion systems, radar, and 5G wireless testers.
Key Specifications
| Specification | Value |
|---|---|
| Package | 64-Pin WQFN (NKD) |
| Operating Temperature Range (°C) | -55 to 105 |
| Maximum Distribution Frequency | 3.2 GHz |
| RMS Jitter (12 kHz to 20 MHz) | 88 fs |
| RMS Jitter (100 Hz to 20 MHz) | 91 fs |
| Noise Floor at 245.76 MHz | -162.5 dBc/Hz |
| Number of Differential Device Clocks from PLL2 | Up to 14 |
| Number of SYSREF Clocks | Up to 7 |
| Output Types | LVPECL, LVDS, HSDS, LCPECL, LVCMOS |
| Supply Voltage | 3.15-V to 3.45-V |
Key Features
- Ultra-low-noise JESD204B compliant clock jitter cleaner
- Dual PLLatinum™ PLL architecture with two integrated low-noise VCOs
- Maximum distribution frequency of 3.2 GHz
- Low RMS jitter: 88 fs (12 kHz to 20 MHz) and 91 fs (100 Hz to 20 MHz)
- Low noise floor: -162.5 dBc/Hz at 245.76 MHz
- Up to 14 differential device clocks from PLL2 and up to 7 SYSREF clocks
- Programmable outputs: LVPECL, LVDS, HSDS, LCPECL, and LVCMOS
- Multi-mode operation: dual PLL, single PLL, and clock distribution
- Automatic and manual switchover modes with hitless switching and LOS
- Integrated low-noise crystal oscillator circuit and holdover mode
- Precision digital delay and dynamically adjustable 25-ps step analog delay
Applications
- High-speed data conversion systems
- Radar systems
- 5G wireless testers
- High-performance clocking systems for traditional logic devices
- Daisy-chain configurations for synchronized clocking across multiple boards
Q & A
- What is the operating temperature range of the LMK04828SNKDTEP?
The operating temperature range is -55 to 105°C.
- What is the maximum distribution frequency of the LMK04828SNKDTEP?
The maximum distribution frequency is 3.2 GHz.
- What types of output signals can the LMK04828SNKDTEP generate?
The device can generate LVPECL, LVDS, HSDS, LCPECL, and LVCMOS output signals.
- How many differential device clocks can the LMK04828SNKDTEP provide from PLL2?
Up to 14 differential device clocks can be provided from PLL2.
- What is the RMS jitter performance of the LMK04828SNKDTEP?
The RMS jitter is 88 fs (12 kHz to 20 MHz) and 91 fs (100 Hz to 20 MHz).
- Does the LMK04828SNKDTEP support JESD204B?
Yes, the device is JESD204B compliant.
- What is the supply voltage range for the LMK04828SNKDTEP?
The supply voltage range is 3.15-V to 3.45-V.
- Can the LMK04828SNKDTEP operate in multiple modes?
Yes, it supports dual PLL, single PLL, and clock distribution modes.
- Does the LMK04828SNKDTEP have integrated low-noise VCOs?
Yes, it features two integrated low-noise VCOs.
- What is the package type of the LMK04828SNKDTEP?
The package type is 64-Pin WQFN (NKD).
