Overview
The DS90CR483AVJDX/NOPB is a 48-bit LVDS (Low Voltage Differential Signaling) Channel Link serializer produced by Texas Instruments. This component is part of the DS90CR483A/DS90CR484A chipset, designed to convert 48 bits of CMOS/TTL data into eight LVDS data streams. It includes a phase-locked transmit clock transmitted in parallel with the data streams over a ninth LVDS link. This device is optimized for high-speed data transmission, addressing issues related to EMI and cable size in wide, high-speed TTL interfaces.
Key Specifications
| Parameter | Min | Typ | Max | Units |
|---|---|---|---|---|
| Supply Voltage (VCC) | 3.0 | 3.3 | 3.6 | V |
| Operating Free Air Temperature (TA) | -10 | +25 | +70 | °C |
| Input Clock (TX) | 33 | - | 112 | MHz |
| Transmitter Supply Current (ICCTW) at 112 MHz | 155 | - | 210 | mA |
| Receiver Supply Current (ICCRW) at 112 MHz | 250 | - | 280 | mA |
| Package Type | - | - | TQFP (NEZ) 100 pins | - |
| Data Throughput at 112 MHz Clock | - | - | 5.38 Gbit/s (672 Mbytes/s) | - |
Key Features
- High-Speed Data Transmission: Supports clock rates up to 112 MHz and provides a data throughput of 5.38 Gbit/s (672 Mbytes/s) per LVDS data channel.
- Cable Drive Enhancement: Includes a user-selectable pre-emphasis feature to counteract cable loading effects and optional DC balancing to reduce Inter-Symbol Interference (ISI).
- Cable Deskew Capability: Deskews long cables to compensate for pair-to-pair skew of up to ±1 LVDS data bit time (up to 80 MHz clock rates).
- Flow Through Pinout: Designed for easy PCB design.
- 5V Tolerant Inputs: Supports 5V tolerant TxIN and control input pins.
- Low Power Consumption: Power down feature minimizes current draw and shuts down PLLs.
Applications
The DS90CR483A/DS90CR484A chipset is ideal for applications requiring high-speed data transmission over long distances, such as in industrial automation, medical imaging, and high-definition video transmission. It is particularly useful in scenarios where EMI and cable size are significant concerns.
Q & A
- What is the maximum clock rate supported by the DS90CR483A? The maximum clock rate supported is 112 MHz.
- How many LVDS data streams are generated by the DS90CR483A? The device generates eight LVDS data streams.
- What is the data throughput at a 112 MHz clock rate? The data throughput is 5.38 Gbit/s (672 Mbytes/s) per LVDS data channel.
- Does the DS90CR483A support cable deskew? Yes, it supports cable deskew to compensate for pair-to-pair skew of up to ±1 LVDS data bit time (up to 80 MHz clock rates).
- What is the purpose of the pre-emphasis feature? The pre-emphasis feature provides additional output current during transitions to counteract cable loading effects.
- How does the DC balancing feature work? DC balancing reduces Inter-Symbol Interference (ISI) on long cable applications.
- What is the package type of the DS90CR483AVJDX/NOPB? The package type is TQFP (NEZ) with 100 pins.
- Is the DS90CR483A 5V tolerant? Yes, it has 5V tolerant TxIN and control input pins.
- How does the power down feature work? The power down feature minimizes current draw and shuts down the PLLs when asserted.
- What are the typical applications of the DS90CR483A/DS90CR484A chipset? Typical applications include industrial automation, medical imaging, and high-definition video transmission.
