Overview
The CDCM61004RHBR/2801 from Texas Instruments is a highly versatile, low-jitter clock generator designed for high-end data communication applications. This device features a fully-integrated voltage-controlled oscillator (VCO) and a phase-locked loop (PLL) that synchronizes the VCO with a low-frequency crystal or LVCMOS input. It provides four universal output buffers that can be configured to be LVPECL, LVDS, or LVCMOS compatible, making it suitable for a variety of wireline and data communication applications such as SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV.
The CDCM61004 operates in a 3.3-V supply environment and is characterized for operation from –40°C to 85°C. It is available in a small, 32-pin, 5-mm × 5-mm VQFN package, which enhances its usability in space-constrained designs.
Key Specifications
| Parameter | Min | Typ | Max | Unit |
|---|---|---|---|---|
| Supply Voltage (VCC) | –0.5 | 4.6 | V | |
| Input Voltage (VIN) | –0.5 | VCC_IN + 0.5 | V | |
| Output Frequency Range | 43.75 | 683.264 | MHz | |
| Output Duty Cycle | 45% | 55% | ||
| Random Jitter (RMS, 10 kHz to 20 MHz) | 0.509 | ps | ||
| Output Skew (LVPECL) | 30 | ps | ||
| Internal PLL Loop Bandwidth | 400 | kHz | ||
| Operating Temperature Range | –40 | 85 | °C | |
| Package Type | VQFN (32-pin) | |||
| Package Size | 5.00 mm × 5.00 mm |
Key Features
- Four universal output buffers configurable as LVPECL, LVDS, or LVCMOS.
- On-chip VCO operates in the frequency range of 1.75 GHz to 2.05 GHz.
- Low-jitter clock driver with random jitter typically at 0.509 ps, RMS (10 kHz to 20 MHz).
- Output frequency selectable by /1, /2, /3, /4, /6, /8 from a single output divider.
- LVCMOS bypass output available to help with crystal loading.
- High-performance PLL core with phase noise typically at –146 dBc/Hz at 5-MHz offset for 625-MHz LVPECL output.
- Output duty cycle corrected to 50% (± 5%).
- Low output skew of 30 ps on LVPECL outputs.
- Divider programming using control pins.
Applications
- High-end datacom applications including SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV.
- Cost-effective high-frequency crystal oscillator replacement.
- Wireline and data communication systems.
- Storage Area Networks (SAN).
Q & A
- What is the CDCM61004RHBR/2801 used for?
The CDCM61004RHBR/2801 is used as a low-jitter clock generator for high-end data communication applications such as SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV.
- What are the output options for the CDCM61004?
The CDCM61004 provides four universal output buffers that can be configured as LVPECL, LVDS, or LVCMOS.
- What is the operating frequency range of the VCO in the CDCM61004?
The on-chip VCO operates in the frequency range of 1.75 GHz to 2.05 GHz.
- What is the typical random jitter performance of the CDCM61004?
The random jitter performance is typically at 0.509 ps, RMS (10 kHz to 20 MHz).
- How is the output frequency selected in the CDCM61004?
The output frequency is selectable by /1, /2, /3, /4, /6, /8 from a single output divider using control pins.
- What is the package type and size of the CDCM61004?
The CDCM61004 is available in a 32-pin VQFN package with a size of 5.00 mm × 5.00 mm.
- What is the operating temperature range of the CDCM61004?
The operating temperature range is from –40°C to 85°C.
- Does the CDCM61004 support LVCMOS bypass output?
Yes, the CDCM61004 supports an LVCMOS bypass output to help with crystal loading.
- What is the phase noise performance of the CDCM61004?
The phase noise is typically at –146 dBc/Hz at 5-MHz offset for 625-MHz LVPECL output.
- How is the output duty cycle managed in the CDCM61004?
The output duty cycle is corrected to 50% (± 5%).
