Overview
The CDCLVD1213RGTR from Texas Instruments is a 1:4 low additive jitter LVDS buffer with an integrated frequency divider. This device is designed to distribute an input clock to four pairs of differential LVDS clock outputs, ensuring low additive jitter and minimal output skew. It supports input signals from LVDS, LVPECL, and CML sources and is optimized for driving 50-Ω transmission lines. The CDCLVD1213 operates in a 2.5-V supply environment and is characterized over an ambient temperature range of –40°C to 85°C. It is packaged in a small 3 mm × 3 mm, 16-pin VQFN package, making it suitable for various high-performance applications.
Key Specifications
| Parameter | Min | Max | Unit | |
|---|---|---|---|---|
| Device Supply Voltage (VCC) | 2.375 | 2.5 | 2.625 | V |
| Ambient Temperature (TA) | –40 | 85 | °C | |
| Clock Frequency | 800 | MHz | ||
| Low Additive Jitter | 152 | fs RMS (10 kHz to 20 MHz) | ||
| Output Skew | 20 | ps (Maximum) | ||
| Differential Output Voltage Magnitude | 250 | 450 | mV | |
| ESD Protection (HBM) | 3000 | V | ||
| ESD Protection (CDM) | 1000 | V | ||
| Package Type | VQFN (16 pins) | |||
| Package Size | 3 mm × 3 mm |
Key Features
- Low additive jitter: < 300 fs RMS in 10 kHz to 20 MHz
- Low output skew: 20 ps (Maximum)
- Selectable divider ratio: 1, 2, or 4
- Universal input accepts LVDS, LVPECL, and CML signals
- Four LVDS outputs, ANSI EIA/TIA-644A standard compatible
- Fail-safe function to prevent random oscillation of outputs in the absence of an input signal
- Input hysteresis to ensure stable operation
- ESD protection exceeds 3 kV HBM and 1 kV CDM
- Industrial temperature range: –40°C to 85°C
Applications
- Telecommunications and Networking
- Medical Imaging
- Test and Measurement Equipment
- Wireless Communications
- General-Purpose Clocking
Q & A
- What is the maximum clock frequency supported by the CDCLVD1213?
The CDCLVD1213 supports clock frequencies up to 800 MHz.
- What types of input signals does the CDCLVD1213 accept?
The CDCLVD1213 accepts LVDS, LVPECL, and CML input signals.
- What is the typical additive jitter of the CDCLVD1213?
The typical additive jitter is 152 fs RMS in the 10 kHz to 20 MHz frequency range.
- What is the output skew of the CDCLVD1213?
The output skew is 20 ps (Maximum).
- Can the CDCLVD1213 be used in industrial temperature environments?
- What is the package type and size of the CDCLVD1213?
The CDCLVD1213 is packaged in a 3 mm × 3 mm, 16-pin VQFN package.
- Does the CDCLVD1213 have ESD protection?
- What are the typical applications of the CDCLVD1213?
The CDCLVD1213 is used in telecommunications, medical imaging, test and measurement equipment, wireless communications, and general-purpose clocking.
- How does the divider function on the CDCLVD1213 work?
The divider on the CDCLVD1213 can be configured to divide the input frequency by a factor of 1, 2, or 4 through the control pin.
- What kind of termination is required for the LVDS outputs of the CDCLVD1213?
Proper LVDS termination for signal integrity over two 50-Ω lines is 100 Ω between the outputs on the receiver end. Either DC-coupled or AC-coupled termination can be used.
