Overview
The CDCLVC1310RHBR, produced by Texas Instruments, is a highly versatile, low-jitter, low-power clock fanout buffer. This device is designed to distribute low-jitter LVCMOS clock outputs to ten outputs, making it suitable for a variety of applications including wireless and wired infrastructure, networking and data communications, medical imaging, portable test and measurement, and high-end audio/video systems. The CDCLVC1310 features a high-performance crystal buffer with an ultralow noise floor of –169 dBc/Hz and additive phase noise/jitter performance of 25 fsRMS (typical).
Key Specifications
| Parameter | Min | Max | Unit | |
|---|---|---|---|---|
| Core Supply Voltage (VDD) | 2.375 | 2.5 | 2.625 | V |
| Output Supply Voltage (VDDO) | 1.35 | 1.5 | 1.65 | V |
| Input Frequency (fIN) | DC | - | 200 | MHz |
| Crystal Frequency | 8 | - | 50 | MHz |
| Output Frequency (fOUT) | - | - | 200 | MHz |
| Total Propagation Delay | - | 2 | - | ns |
| Output Skew | - | 30 | - | ps |
| Additive Jitter | - | 25 | - | fsRMS |
| Ambient Temperature (TA) | -40 | - | 85 | °C |
| Junction Temperature (TJ) | - | - | 125 | °C |
Key Features
- High-performance crystal buffer with ultralow noise floor of –169 dBc/Hz
- Additive phase noise/jitter performance of 25 fsRMS (typical)
- Level translation with 3.3-V or 2.5-V core and 3.3-V, 2.5-V, 1.8-V, or 1.5-V output supply
- Supports differential and single-ended input signals (LVPECL, LVDS, HCSL, SSTL, LVCMOS)
- 10 single-ended LVCMOS outputs operating up to 200 MHz
- Synchronous and glitch-free output enable available
- Offered in a 32-pin QFN package with an industrial temperature range of –40°C to 85°C
- Can overdrive crystal input with LVCMOS signal up to 50 MHz
Applications
- Wireless and wired infrastructure
- Networking and data communications
- Medical imaging
- Portable test and measurement
- High-end audio/video systems
Q & A
- What is the primary function of the CDCLVC1310?
The CDCLVC1310 is a low-jitter, low-power clock fanout buffer that distributes low-jitter LVCMOS clock outputs to ten outputs.
- What are the supported input signal types for the CDCLVC1310?
The device supports differential and single-ended input signals including LVPECL, LVDS, HCSL, SSTL, and LVCMOS.
- What is the range of the core supply voltage (VDD) for the CDCLVC1310?
The core supply voltage (VDD) ranges from 2.375 V to 2.625 V for 2.5 V operation and from 3.135 V to 3.465 V for 3.3 V operation.
- What is the maximum output frequency supported by the CDCLVC1310?
The device supports output frequencies up to 200 MHz.
- What is the typical additive jitter performance of the CDCLVC1310?
The additive jitter performance is 25 fsRMS (typical).
- What is the noise floor of the CDCLVC1310?
The noise floor is –169 dBc/Hz.
- What are the supported output supply voltages for the CDCLVC1310?
The output supply voltages can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V.
- What is the package type and size of the CDCLVC1310?
The device is offered in a 32-pin QFN package with dimensions of 5-mm × 5-mm.
- What is the operating temperature range of the CDCLVC1310?
The device operates over an industrial temperature range of –40°C to 85°C.
- Can the CDCLVC1310 overdrive a crystal input with an LVCMOS signal?
Yes, the CDCLVC1310 can overdrive a crystal input with an LVCMOS signal up to 50 MHz.
