Overview
The PX1011B-EL1/G,557 is a high-performance, low-power PCI Express stand-alone PHY (Physical Layer) developed by NXP USA Inc. This component is designed to handle the low-level PCI Express protocol and signaling, ensuring compliance with the PCI Express Base Specification, Rev. 1.0a and Rev. 1.1. The PX1011B is optimized for single-lane PCI Express applications, offering advanced features such as Clock and Data Recovery (CDR), data serialization and de-serialization, 8b/10b encoding, and elastic buffer management.
Key Specifications
| Parameter | Conditions | Min | Typ | Max | Unit |
|---|---|---|---|---|---|
| VDDD1 (digital supply voltage 1 for JTAG I/O) | 3.0 | 3.3 | 3.6 | V | |
| VDDD2 (digital supply voltage 2 for SSTL_2 I/O) | 2.3 | 2.5 | 2.7 | V | |
| VDDD3 (digital supply voltage 3 for core) | 1.15 | 1.2 | 1.3 | V | |
| VDD (supply voltage for high-speed serial I/O and PVT) | 1.15 | 1.2 | 1.3 | V | |
| VDDA1 (analog supply voltage 1 for serializer) | 1.15 | 1.2 | 1.3 | V | |
| VDDA2 (analog supply voltage 2 for serializer) | 3.0 | 3.3 | 3.6 | V | |
| fclk(ref) (reference clock frequency) | 99.97 | 100 | 100.03 | MHz | |
| Tamb (ambient temperature operating) | Commercial | 0 | +70 | °C | |
| Tamb (ambient temperature operating) | Industrial | -40 | +85 | °C |
Key Features
- Compliant to PCI Express Base Specification 1.1
- Single PCI Express 2.5 Gbit/s lane
- Clock and Data Recovery (CDR) from serial stream
- Serializer and De-serializer (SerDes)
- Receiver detection
- 8b/10b coding and decoding, elastic buffer, and word alignment
- Supports loopback and direct disparity control for transmitting compliance patterns
- Lane polarity inversion support
- Low jitter and Bit Error Rate (BER)
- PHY/MAC interface based on Intel PHY Interface for PCI Express architecture v1.0 (PIPE), adapted for off-chip with additional synchronous clock signals (PXPIPE)
- 8-bit parallel data interface for transmit and receive at 250 MHz with SSTL_2 class I signaling
- Advanced power management functions
Applications
The PX1011B-EL1/G,557 is suitable for various applications requiring high-speed PCI Express interfaces, including:
- Embedded systems
- Industrial control systems
- Automotive systems (with the AEC-Q100 compliant version PX1011B-EL1/Q900)
- Data communication equipment
- High-performance computing systems
Q & A
- What is the primary function of the PX1011B-EL1/G,557?
The primary function is to handle the low-level PCI Express protocol and signaling, converting digital data into electrical signals and vice versa.
- What PCI Express specification does the PX1011B comply with?
The PX1011B complies with the PCI Express Base Specification, Rev. 1.0a and Rev. 1.1.
- What is the data rate of the PX1011B-EL1/G,557?
The data rate is 2.5 Gbit/s per lane.
- What type of interface does the PX1011B use?
The PX1011B uses an 8-bit parallel data interface for transmit and receive at 250 MHz with SSTL_2 class I signaling.
- Does the PX1011B support advanced power management?
Yes, it supports advanced power management functions.
- What are the operating temperature ranges for the PX1011B?
The operating temperature ranges are from 0°C to +70°C for commercial and from -40°C to +85°C for industrial applications.
- Is the PX1011B-EL1/G,557 AEC-Q100 compliant?
No, but an AEC-Q100 compliant version (PX1011B-EL1/Q900) is available.
- What is the package type of the PX1011B-EL1/G,557?
The package type is 81-LFBGA (9x9).
- Does the PX1011B support loopback and disparity control?
Yes, it supports loopback and direct disparity control for transmitting compliance patterns.
- What is the significance of the PXPIPE interface?
The PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE) specification, adapted for off-chip applications with additional synchronous clock signals.
