Overview
The MIMXRT595SFFOC is a part of the i.MX RT500 family of crossover microcontrollers (MCUs) produced by NXP USA Inc. This dual-core device combines an ARM Cortex-M33 core with a Cadence Xtensa Fusion F1 DSP, making it highly suitable for low-power wearable and consumer IoT applications. The MCU is designed with a security-by-design approach, aligning with NXP's EdgeLock Assurance program to meet industry standards for security.
Key Specifications
| Specification | Details |
|---|---|
| Processor Cores | Dual-core: ARM Cortex-M33 and Cadence Xtensa Fusion F1 DSP |
| Operating Frequency | Up to 275 MHz for both Cortex-M33 and Fusion F1 DSP |
| Memory | Up to 5 MB SRAM, 192 KB ROM, 16 kbits OTP fuses |
| Communication Interfaces | Up to 9 configurable universal serial interface modules (Flexcomm Interfaces), including USART, I2C, SPI, I2S, and I3C |
| Storage Interfaces | Two FlexSPI interfaces, two SD/eMMC memory card interfaces |
| Analog Peripherals | 12-bit ADC with sampling rates of 1 Msamples/sec, enhanced ADC controller |
| Graphics and Multimedia | 2D Vector Graphics Processing Unit, LCD Display Interface, MIPI DSI Interface |
| GPIO | Up to 136 general purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors |
| Package | 249-FOWLP (7x7 mm) |
Key Features
- Dual-core architecture with ARM Cortex-M33 and Cadence Xtensa Fusion F1 DSP for enhanced performance and low power consumption.
- Rich set of peripherals including multiple serial interfaces, high-speed SPI, and I2C interfaces.
- Integrated 2D Vector Graphics Processing Unit and LCD Display Interface for graphics and multimedia applications.
- MIPI DSI Interface with on-chip PHY supporting high transfer rates.
- Advanced security features including SRAM PUF, AES256, and HASH, as part of the EdgeLock Assurance program.
- Support for various boot modes from High-speed SPI, FlexSPI Flash, HS USB, I2C, UART, or eMMC via on-chip bootloader software.
- SmartDMA controller with dedicated code RAM and general purpose DMA engines.
Applications
- Low-power wearable devices such as smartwatches and fitness trackers.
- Consumer IoT devices including smart home appliances and personal care products.
- Industrial automation and control systems requiring low power and high performance.
- Audio and voice processing applications leveraging the I2S interface and digital microphone support.
- Display and graphics-intensive applications such as smart displays and interactive kiosks.
Q & A
- What is the primary processor core in the MIMXRT595SFFOC?
The primary processor core is the ARM Cortex-M33, accompanied by a Cadence Xtensa Fusion F1 DSP. - What is the maximum operating frequency of the MCU?
The maximum operating frequency is up to 275 MHz for both the Cortex-M33 and the Fusion F1 DSP. - What types of memory does the MIMXRT595SFFOC support?
The MCU supports up to 5 MB SRAM, 192 KB ROM, and 16 kbits OTP fuses. - What communication interfaces are available on the MIMXRT595SFFOC?
The MCU features up to 9 configurable universal serial interface modules, including USART, I2C, SPI, I2S, and I3C. - Does the MIMXRT595SFFOC support graphics and multimedia processing?
Yes, it includes a 2D Vector Graphics Processing Unit, LCD Display Interface, and MIPI DSI Interface. - What is the package type of the MIMXRT595SFFOC?
The package type is 249-FOWLP (7x7 mm). - What security features are integrated into the MIMXRT595SFFOC?
The MCU includes SRAM PUF, AES256, and HASH as part of the EdgeLock Assurance program. - What development ecosystem supports the MIMXRT595SFFOC?
The MCU is supported by the MCUXpresso ecosystem, which includes an SDK, a choice of IDEs, and secure provisioning and configuration tools. - Can the MIMXRT595SFFOC be used in wearable devices?
Yes, it is designed for low-power wearable and consumer IoT applications. - How many GPIO pins does the MIMXRT595SFFOC have?
The MCU has up to 136 general purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors.
