Overview
The LTC2240IUP-12#PBF is a high-performance, 12-bit analog-to-digital converter (ADC) designed by Analog Devices Inc. This component is part of the LTC2240 family and is optimized for digitizing high-frequency, wide dynamic range signals. It operates at a sampling rate of 170 Msps, making it suitable for demanding communications applications. The ADC features excellent AC performance, including a signal-to-noise ratio (SNR) of 65.6 dB and a spurious free dynamic range (SFDR) of 80 dB. Additionally, it has ultralow jitter of 95 fs RMS, enabling IF undersampling with excellent noise performance.
Key Specifications
| Parameter | Value |
|---|---|
| Resolution | 12 bits |
| Sampling Rate | 170 Msps |
| Signal-to-Noise Ratio (SNR) | 65.6 dB |
| Spurious Free Dynamic Range (SFDR) | 80 dB |
| Full Power Bandwidth S/H | 1.2 GHz |
| Supply Voltage | Single 2.5V |
| Power Dissipation | 445 mW |
| Output Formats | LVDS, CMOS, or Demultiplexed CMOS |
| Input Ranges | ±0.5V or ±1V |
| Integral Non-Linearity (INL) | ±0.6 LSB (typ) |
| Differential Non-Linearity (DNL) | ±0.4 LSB (typ) |
| Package | 64-Pin QFN (9mm x 9mm x 0.75mm w/ EP) |
Key Features
- No missing codes over temperature.
- Optional clock duty cycle stabilizer for high performance over a wide range of clock duty cycles.
- Shutdown and nap modes for power management.
- Data ready output clock.
- Pin compatible family with other LTC2240 series ADCs.
- Separate output power supply allowing CMOS output swing to range from 0.5V to 2.625V.
- ENC+ and ENC- inputs can be driven differentially or single-ended with various signal types (sine wave, PECL, LVDS, TTL, or CMOS).
Applications
- Wireless and Wired Broadband Communication.
- Cable Head-End Systems.
- Power Amplifier Linearization.
- Communications Test Equipment.
Q & A
- What is the sampling rate of the LTC2240IUP-12#PBF?
The sampling rate of the LTC2240IUP-12#PBF is 170 Msps.
- What is the signal-to-noise ratio (SNR) of this ADC?
The SNR of the LTC2240IUP-12#PBF is 65.6 dB.
- What are the available output formats for this ADC?
The output formats available are LVDS, CMOS, or demultiplexed CMOS.
- What are the input range options for this ADC?
The input ranges can be set to ±0.5V or ±1V.
- Does this ADC have any power-saving modes?
- What is the package type and size of this ADC?
The package is a 64-Pin QFN (9mm x 9mm x 0.75mm w/ EP).
- Can the ENC+ and ENC- inputs be driven differentially or single-ended?
- What is the typical power dissipation of this ADC?
- Is there an optional clock duty cycle stabilizer available?
- What are some common applications for this ADC?
