Overview
The ADSP-TS101S TigerSHARC processor, produced by Analog Devices Inc., is an ultrahigh-performance, Static Superscalar processor optimized for large signal processing tasks and communications infrastructure. This processor combines wide memory widths with dual computation blocks, supporting various bit-widths for floating-point and fixed-point processing, setting a new standard for digital signal processors. The ADSP-TS101S operates at 300 MHz with a 3.3 ns instruction cycle time and is designed to execute up to four instructions per cycle, performing 24 fixed-point or six floating-point operations simultaneously.
Key Specifications
| Specification | Value |
|---|---|
| Operating Frequency | 300 MHz |
| Instruction Cycle Time | 3.3 ns |
| Internal SRAM Memory | 6 Mbits (3 blocks of 2M bits each) |
| Package Options | 19 mm × 19 mm (484-ball) CSP_BGA or 27 mm × 27 mm (625-ball) PBGA |
| Compute Blocks | Dual computation blocks with ALU, multiplier, shifter, and register file |
| Integer ALUs | Dual integer ALUs with 31-word register files each |
| Internal Data Buses | Three independent 128-bit-wide internal data buses |
| Internal Memory Bandwidth | 14.4 Gbytes per second |
| Operating Temperature Range | -40°C to 85°C |
| RoHS Compliance | Yes |
Key Features
- Dual computation blocks supporting 32- and 40-bit floating-point and 8-, 16-, 32-, and 64-bit fixed-point processing.
- Static Superscalar architecture allowing up to four instructions per cycle, performing 24 fixed-point or six floating-point operations.
- Single-instruction, multiple-data (SIMD) features enabling 2.4 billion 40-bit MACs or 600 million 80-bit MACs per second.
- Integrated I/O includes 14-channel DMA controller, external port, 4 link ports, SDRAM controller, programmable flag pins, 2 timers, and timer expired pin.
- 1149.1 IEEE compliant JTAG test access port for on-chip emulation.
- On-chip arbitration for glueless multiprocessing with up to 8 TigerSHARC processors on a bus.
- Flexible instruction set and high-level language-friendly DSP architecture easing DSP programming.
Applications
The ADSP-TS101S TigerSHARC processor is optimized for large signal processing tasks and communications infrastructure. It is particularly suited for:
- Telecommunications infrastructure
- High-performance DSP applications
- Multiprocessor systems with low communications overhead
- Imaging and video processing
Q & A
- What is the operating frequency of the ADSP-TS101S processor? The ADSP-TS101S operates at 300 MHz.
- What is the instruction cycle time of the ADSP-TS101S? The instruction cycle time is 3.3 ns.
- How much internal SRAM memory does the ADSP-TS101S have? The ADSP-TS101S has 6 Mbits of internal SRAM memory, divided into three blocks of 2M bits each.
- What are the package options for the ADSP-TS101S? The ADSP-TS101S is available in 19 mm × 19 mm (484-ball) CSP_BGA or 27 mm × 27 mm (625-ball) PBGA packages.
- What types of computations can the ADSP-TS101S perform? The ADSP-TS101S supports 32- and 40-bit floating-point and 8-, 16-, 32-, and 64-bit fixed-point processing.
- What is the internal memory bandwidth of the ADSP-TS101S? The internal memory bandwidth is 14.4 Gbytes per second.
- Is the ADSP-TS101S RoHS compliant? Yes, the ADSP-TS101S is RoHS compliant.
- What is the operating temperature range of the ADSP-TS101S? The operating temperature range is -40°C to 85°C.
- What kind of I/O does the ADSP-TS101S support? The ADSP-TS101S supports integrated I/O including a 14-channel DMA controller, external port, 4 link ports, SDRAM controller, programmable flag pins, 2 timers, and a timer expired pin.
- Can the ADSP-TS101S be used in multiprocessor systems? Yes, the ADSP-TS101S supports glueless multiprocessing with up to 8 TigerSHARC processors on a bus).
