Overview
The ADSP-21160NKB-100 is a high-performance 32-bit SHARC (Super Harvard Architecture Single-Chip Computer) Digital Signal Processor (DSP) produced by Analog Devices Inc. It is the second iteration of the ADSP-21160 series, fabricated in a 0.18 micron CMOS process, which offers higher performance and lower power consumption compared to its predecessor, the ADSP-21160M. This DSP is optimized for high-performance DSP applications and is application source code compatible with first-generation ADSP-2106x SHARC DSPs in Single Instruction, Single Data (SISD) mode, although some code changes are necessary to leverage its Single Instruction, Multiple Data (SIMD) capability.
Key Specifications
| Specification | Value |
|---|---|
| Core Instruction Rate | 100 MHz (10.5 ns) |
| Peak Performance | 570 MFLOPS |
| Sustained Performance (Based on FIR) | 380 MFLOPS |
| Computational Units | Two 32-bit IEEE floating-point computation units, each with a multiplier, ALU, shifter, and register file |
| Memory | 4M-bit dual-ported on-chip SRAM |
| Package | 400-Ball 27 × 27 mm Metric PBGA |
| Power Supplies | Separate power supply connections for internal (VDDINT), external (VDDEXT), and analog (AVDD and AGND) power supplies |
| Operating Temperature | 0 to 85°C |
| Peripherals | Integrated I/O processor, two serial ports, six link ports, external parallel bus, and glueless multiprocessing features |
Key Features
- SIMD Architecture: Provides two computational processing elements for concurrent execution and code compatibility at the assembly level with the ADSP-2106x SHARC DSP family.
- Single-Cycle Instruction Execution: Including SIMD operations in both computational units.
- Dual Data Address Generators (DAGs): With modulo and bit-reverse addressing.
- Zero-Overhead Looping: And single-cycle loop setup for efficient program sequencing.
- IEEE 1149.1 JTAG Standard Test Access Port and On-Chip Emulation: For comprehensive testing and debugging capabilities.
- Integrated Peripherals: Includes an integrated I/O processor, 4M bits of on-chip dual-ported SRAM, and various ports (serial, link, external bus).
Applications
- Medical Applications: Suitable for medical imaging, diagnostic equipment, and other medical devices requiring high-performance DSP capabilities.
- Military Applications: Used in various military systems that require robust and high-performance signal processing.
- Communications: Ideal for communication systems, including wireless communication and network infrastructure.
- Industrial Applications: Applied in industrial control systems, motor control, and other industrial automation tasks.
- Professional Audio: Utilized in professional audio equipment and systems that demand high-quality signal processing.
Q & A
- What is the core instruction rate of the ADSP-21160N?
The core instruction rate of the ADSP-21160N is 100 MHz (10.5 ns).
- What is the peak performance of the ADSP-21160N?
The peak performance of the ADSP-21160N is 570 MFLOPS.
- How many computational units does the ADSP-21160N have?
The ADSP-21160N has two 32-bit IEEE floating-point computation units.
- What type of memory does the ADSP-21160N have?
The ADSP-21160N has 4M bits of on-chip dual-ported SRAM.
- What is the package type of the ADSP-21160N?
The ADSP-21160N comes in a 400-Ball 27 × 27 mm Metric PBGA package.
- Is the ADSP-21160N compatible with previous SHARC DSPs?
Yes, the ADSP-21160N is application source code compatible with first-generation ADSP-2106x SHARC DSPs in SISD mode.
- What are the key peripherals of the ADSP-21160N?
The key peripherals include an integrated I/O processor, two serial ports, six link ports, and an external parallel bus.
- What is the operating temperature range of the ADSP-21160N?
The operating temperature range of the ADSP-21160N is 0 to 85°C.
- Does the ADSP-21160N support multiprocessing?
Yes, the ADSP-21160N supports glueless multiprocessing features.
- What development tools are available for the ADSP-21160N?
The ADSP-21160N is supported by the CrossCore Embedded Studio (CCES), a world-class integrated development environment (IDE) for ADI processor families.
