Overview
The ADAU7112ACBZR7, produced by Analog Devices Inc., is a stereo pulse density modulation (PDM) to pulse code modulation (PCM) converter. This device converts stereo PDM bitstreams from sources such as digital microphones into a single PCM output stream. It supports both inter-IC serial (I2S) and time domain multiplexed (TDM) output formats, making it versatile for various audio applications.
Key Specifications
| Parameter | Min | Typ | Max | Unit |
|---|---|---|---|---|
| Output Sampling Rate (fS) | 4 kHz | - | 96 kHz | - |
| Bit Resolution | - | - | 24 Bits | - |
| Signal-to-Noise Ratio (SNR) | - | - | 126 dB A-weighted | - |
| Bit Clock Frequency (fBCLK) | 0.256 MHz | - | 24.576 MHz | - |
| PDM_CLK Frequency | 0.256 MHz | - | 6.144 MHz | - |
| Digital Core Voltage (DVDD) | 1.10 V | - | 1.98 V | - |
| Input/Output Supply Voltage (IOVDD) | 1.70 V | - | 3.63 V | - |
| Operating Current at 48 kHz and 1.8 V | - | 0.36 mA | - | - |
| Shutdown Current | - | 4 μA | - | - |
| Package Type | - | - | 9-Ball WLCSP (1.26mm x 1.26mm x 0.4mm pitch) | - |
| Temperature Range | -40°C | - | +85°C | - |
Key Features
- 2 channels of PDM audio inputs from digital microphones
- 64× decimation ratio of PDM to PCM audio data
- Automatic PDM clock generation
- Automatic power-down when BCLK is removed
- Slave I2S or TDM output interface with up to TDM-16 supported
- Configurable TDM slots
- Power-on reset
- Low operating current and shutdown current
Applications
- Mobile computing
- Portable electronics
- Consumer electronics
- Professional electronics
Q & A
- What is the primary function of the ADAU7112ACBZR7?
The ADAU7112ACBZR7 converts stereo pulse density modulation (PDM) bitstreams into a single pulse code modulation (PCM) output stream. - What are the supported output formats?
The device supports both inter-IC serial (I2S) and time domain multiplexed (TDM) output formats. - What is the bit resolution of the ADAU7112ACBZR7?
The bit resolution is 24 bits. - What is the signal-to-noise ratio (SNR) of the ADAU7112ACBZR7?
The SNR is 126 dB A-weighted. - What are the supported bit clock rates?
The supported bit clock rates are 64×, 128×, 192×, 256×, 384×, and 512× the output sampling rate. - How does the device handle power-down?
The device automatically enters a low power state when the bit clock or frame synchronization is removed and resumes operation when the clocks are restored. - What is the operating temperature range of the ADAU7112ACBZR7?
The operating temperature range is from -40°C to +85°C. - What type of package does the ADAU7112ACBZR7 come in?
The device is packaged in a 9-ball wafer level chip scale package (WLCSP) with a 1.26 mm x 1.26 mm x 0.4 mm pitch. - What are some typical applications of the ADAU7112ACBZR7?
Typical applications include mobile computing, portable electronics, consumer electronics, and professional electronics. - How does the device manage PDM clock generation?
The device generates the PDM clock automatically based on the input sampling rate.
