Overview
The AD9656BCPZRL7-125 is a quad, 16-bit, 125 MSPS (mega-samples per second) analog-to-digital converter (ADC) produced by Analog Devices Inc. This device is designed for low cost, low power, small size, and ease of use, making it ideal for applications where dynamic performance and compact packaging are critical. The ADC operates on a single 1.8 V power supply and supports LVPECL-, CMOS-, and LVDS-compatible sample rate clocks. It features an on-chip sample and hold circuit and is optimized for high-speed imaging, medical imaging, and various radio receiver applications.
Key Specifications
| Parameter | Value | Unit |
|---|---|---|
| Resolution | 16-bit | |
| Sample Rate | Up to 125 MSPS | |
| Power Supply | 1.8 V | |
| Power Consumption per Channel | 197 mW at 125 MSPS (two lanes) | |
| Analog Input Range | 2.0 V p-p to 2.8 V p-p | |
| Analog Input Bandwidth | 650 MHz | |
| DNL (VREF = 1.4 V) | ±0.6 LSB | |
| INL (VREF = 1.4 V) | ±4.5 LSB | |
| SNR at 16 MHz (VREF = 1.4 V) | 79.9 dBFS | |
| SNR at 64 MHz (VREF = 1.4 V) | 78.1 dBFS | |
| SFDR to Nyquist (VREF = 1.4 V) | 86 dBc | |
| Operating Temperature Range | −40°C to +85°C | |
| Package Type | 56-lead LFCSP |
Key Features
- Flexible analog input range: 2.0 V p-p to 2.8 V p-p
- Low power operation: 197 mW per channel at 125 MSPS (two lanes)
- JESD204B Subclass 1 coded serial digital outputs
- Serial port control and SPI interface
- Full chip and individual channel power-down modes
- Built-in and custom digital test pattern generation
- Multichip sync and clock divider
- Standby mode
- Configurable JESD204B output block supporting up to 8.0 Gbps per lane
- On-chip phase-locked loop (PLL) for ADC sampling clock multiplication
Applications
- Medical imaging (e.g., ultrasound, MRI)
- High speed imaging
- Quadrature radio receivers
- Diversity radio receivers
- Portable test equipment
Q & A
- What is the resolution and sample rate of the AD9656BCPZRL7-125?
The AD9656BCPZRL7-125 is a 16-bit ADC with a sample rate of up to 125 MSPS.
- What is the power supply requirement for the AD9656BCPZRL7-125?
The device operates on a single 1.8 V power supply.
- What is the analog input range of the AD9656BCPZRL7-125?
The analog input range is 2.0 V p-p to 2.8 V p-p.
- What is the power consumption per channel at 125 MSPS?
The power consumption per channel is 197 mW at 125 MSPS (two lanes).
- What are the key features of the JESD204B output block in the AD9656BCPZRL7-125?
The JESD204B output block supports up to 8.0 Gbps per lane and configurations of one, two, and four lanes.
- Does the AD9656BCPZRL7-125 support individual channel power-down?
Yes, the device supports individual channel power-down, consuming less than 14 mW when all channels are disabled.
- What is the operating temperature range of the AD9656BCPZRL7-125?
The operating temperature range is −40°C to +85°C.
- What package type is the AD9656BCPZRL7-125 available in?
The device is available in a 56-lead LFCSP package.
- What are some common applications of the AD9656BCPZRL7-125?
Common applications include medical imaging, high speed imaging, quadrature radio receivers, diversity radio receivers, and portable test equipment.
- Does the AD9656BCPZRL7-125 have built-in digital test pattern generation?
Yes, the device includes built-in and custom digital test pattern generation capabilities.
