Overview
The AD9250BCPZ-170, produced by Analog Devices Inc., is a dual, 14-bit analog-to-digital converter (ADC) designed to support communications applications where low cost, small size, wide bandwidth, and versatility are essential. This ADC features a multistage, differential pipelined architecture with integrated output error correction logic and wide bandwidth inputs supporting various user-selectable input ranges. An integrated voltage reference simplifies design considerations, and a duty cycle stabilizer ensures excellent performance by compensating for variations in the ADC clock duty cycle.
Key Specifications
| Parameter | Temperature | Min | Typ | Max | Unit |
|---|---|---|---|---|---|
| Resolution | Full | 14 | 14 | 14 | Bits |
| Offset Error | Full | -16 | - | +16 | mV |
| Gain Error | Full | -6 | - | +2.5 | %FSR |
| Differential Nonlinearity (DNL) | Full | ±0.75 | ±0.75 | ±0.75 | LSB |
| Integral Nonlinearity (INL) | Full | ±2.1 | ±2.1 | ±3.5 | LSB |
| Sampling Speed | - | - | - | 170 MSPS | - |
| Input Span | Full | - | - | 1.75 | µA |
| Input Capacitance | Full | - | - | 1 pF | - |
| Input Resistance | Full | 12 kΩ | 16 kΩ | 20 kΩ | - |
| Operating Temperature | - | -40°C | - | +85°C | - |
| Package Type | - | - | - | 48-Lead LFCSP | - |
Key Features
- Integrated dual, 14-bit ADC with sampling speeds of up to 170 MSPS.
- Configurable JESD204B output block supporting up to 5 Gbps per lane.
- On-chip phase-locked loop (PLL) for ADC sampling clock multiplication.
- Optional RF clock input to ease system board design.
- Proprietary differential input maintaining excellent SNR performance for input frequencies up to 400 MHz.
- Operation from a single 1.8 V power supply.
- Standard serial port interface (SPI) for controlling various product features and functions.
- Flexible power-down options for significant power savings.
- Programmable overrange level detection via dedicated fast detect pins.
Applications
The AD9250BCPZ-170 is designed to support a variety of communications applications, including:
- Wireless infrastructure and base stations
- Software-defined radios
- Radar and electronic warfare systems
- Medical imaging and diagnostic equipment
- High-speed data acquisition systems
The device's versatility, low cost, small size, and wide bandwidth make it an ideal choice for these and other applications requiring high-performance ADCs.
Q & A
- What is the resolution of the AD9250BCPZ-170 ADC?
The AD9250BCPZ-170 has a resolution of 14 bits.
- What are the sampling speeds supported by the AD9250BCPZ-170?
The AD9250BCPZ-170 supports sampling speeds of up to 170 MSPS.
- What type of output interface does the AD9250BCPZ-170 use?
The AD9250BCPZ-170 uses a JESD204B high-speed serial interface.
- What is the operating temperature range of the AD9250BCPZ-170?
The operating temperature range is from -40°C to +85°C.
- What is the package type of the AD9250BCPZ-170?
The AD9250BCPZ-170 is available in a 48-lead LFCSP package.
- Does the AD9250BCPZ-170 support power-down options?
Yes, the AD9250BCPZ-170 supports flexible power-down options for significant power savings.
- How is the AD9250BCPZ-170 programmed and controlled?
The AD9250BCPZ-170 is programmed and controlled using a 3-wire SPI-compatible serial interface.
- What is the purpose of the integrated PLL in the AD9250BCPZ-170?
The integrated PLL multiplies the ADC sampling clock to produce the corresponding JESD204B data rate clock.
- Does the AD9250BCPZ-170 support overrange level detection?
Yes, the AD9250BCPZ-170 supports programmable overrange level detection via dedicated fast detect pins.
- Is there an evaluation board available for the AD9250BCPZ-170?
Yes, the AD9250-250EBZ is an evaluation board available for the AD9250, which provides all the necessary support circuitry to operate the device in various modes and configurations.
