Overview
The AD9245BCPZ-40, manufactured by Analog Devices Inc., is a high-performance, monolithic 14-bit analog-to-digital converter (ADC) designed for a wide range of applications. It operates from a single 3 V power supply and features a separate digital output driver supply to accommodate 2.5 V and 3.3 V logic families. The AD9245 uses a multistage differential pipelined architecture with output error correction logic, ensuring 14-bit accuracy and no missing codes over the full operating temperature range of –40°C to +85°C. This ADC is particularly suited for applications in communications, imaging, and medical ultrasound due to its high performance, low power consumption, and flexible input configurations.
Key Specifications
| Parameter | Min | Typ | Max | |
|---|---|---|---|---|
| Maximum Conversion Rate | 20 MSPS | 40 MSPS | 65 MSPS | 80 MSPS |
| Minimum Conversion Rate | 1 MSPS | - | - | - |
| Clock Period | 50.0 ns | 25.0 ns | 15.4 ns | 12.5 ns |
| Clock Pulse Width High | 15.0 ns | 8.8 ns | 6.2 ns | 4.6 ns |
| Clock Pulse Width Low | 15.0 ns | 8.8 ns | 6.2 ns | 4.6 ns |
| Output Delay (tPD) | 3.5 ns | - | - | 4.2 ns |
| Pipeline Delay (Latency) | 7 Cycles | - | - | - |
| Aperture Delay (tA) | 1.0 ns | - | - | - |
| Aperture Uncertainty Jitter (tJ) | 0.5 ps rms | - | - | 0.3 ps rms |
| Wake-Up Time | 3.0 ms | - | - | 7.0 ms |
| Power Consumption | 90 mW @ 20 MSPS | 165 mW @ 40 MSPS | 300 mW @ 65 MSPS | 366 mW @ 80 MSPS |
| SNR | - | - | - | 72.7 dBc @ 80 MSPS |
| SFDR | - | - | - | 83.0 dBc @ 80 MSPS |
| DNL | - | - | - | ±0.5 LSB @ 80 MSPS |
Key Features
- Single 3 V power supply operation (2.7 V to 3.6 V)
- Low power consumption: 90 mW at 20 MSPS, 165 mW at 40 MSPS, 300 mW at 65 MSPS, and 366 mW at 80 MSPS
- High signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR): SNR = 72.7 dBc and SFDR = 83.0 dBc at 80 MSPS
- Differential input with 500 MHz bandwidth and on-chip reference and sample-and-hold amplifier
- Differential nonlinearity (DNL) of ±0.5 LSB at 80 MSPS
- Flexible analog input range: 1 V p-p to 2 V p-p, with offset binary or twos complement data format
- Clock duty-cycle stabilizer (DCS) for maintaining ADC performance over a wide range of clock pulse widths
- Pin-compatible with AD9215, AD9235, and AD9236 for simplified migration
- Available in a 32-lead LFCSP package
Applications
- Medical imaging equipment
- IF sampling in communications receivers (WCDMA, CDMA-One, CDMA-2000, and TDS-CDMA)
- Battery-powered instruments
- Hand-held scopemeters
- Spectrum analyzers
- Power-sensitive military applications
Q & A
- What is the maximum conversion rate of the AD9245BCPZ-40?
The maximum conversion rate of the AD9245BCPZ-40 is 80 MSPS. - What is the power consumption of the AD9245BCPZ-40 at different conversion rates?
The power consumption is 90 mW at 20 MSPS, 165 mW at 40 MSPS, 300 mW at 65 MSPS, and 366 mW at 80 MSPS. - What is the signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) of the AD9245BCPZ-40 at 80 MSPS?
The SNR is 72.7 dBc and the SFDR is 83.0 dBc at 80 MSPS. - What is the differential nonlinearity (DNL) of the AD9245BCPZ-40 at 80 MSPS?
The DNL is ±0.5 LSB at 80 MSPS. - What types of input configurations are supported by the AD9245BCPZ-40?
The AD9245BCPZ-40 supports differential and single-ended input configurations with a bandwidth of 500 MHz. - Is the AD9245BCPZ-40 pin-compatible with other ADC models?
Yes, it is pin-compatible with the AD9215, AD9235, and AD9236. - What is the operating temperature range of the AD9245BCPZ-40?
The operating temperature range is –40°C to +85°C. - What package type is the AD9245BCPZ-40 available in?
The AD9245BCPZ-40 is available in a 32-lead LFCSP package. - What are some of the key applications of the AD9245BCPZ-40?
Key applications include medical imaging equipment, IF sampling in communications receivers, battery-powered instruments, hand-held scopemeters, spectrum analyzers, and power-sensitive military applications. - Does the AD9245BCPZ-40 have a clock duty-cycle stabilizer?
Yes, it features a clock duty-cycle stabilizer (DCS) to maintain ADC performance over a wide range of clock pulse widths.
