Overview
The AD6655BCPZ-150, produced by Analog Devices Inc., is a mixed-signal intermediate frequency (IF) receiver. It features dual 14-bit analog-to-digital converters (ADCs) with sampling rates of up to 150 MSPS. This component is designed to support communications applications where low cost, small size, and versatility are critical. The AD6655 integrates a wideband digital downconverter (DDC) and various signal processing stages, including a 32-bit frequency translator, a half-band decimating filter, a fixed FIR filter, and an fADC/8 fixed-frequency NCO. This integration simplifies the system design and reduces interconnection parasitics.
Key Specifications
Parameter | AD6655-150 | Unit |
---|---|---|
Resolution | 14 | Bits |
Sampling Rate | Up to 150 | MSPS |
Offset Error | ±0.2 to ±0.6 | % FSR |
Gain Error | −3.6 to −0.1 | % FSR |
Temperature Drift (Offset Error) | ±15 | ppm/°C |
Temperature Drift (Gain Error) | ±95 | ppm/°C |
Internal Voltage Reference Output Voltage Error (1 V Mode) | ±5 to ±18 | mV |
Input-Referred Noise (VREF = 1.0 V, 25°C) | 0.85 | LSB rms |
Differential Clock Inputs (CLK+, CLK−) Logic Compliance | CMOS/LVDS/LVPECL | |
Differential Input Voltage | 0.2 to 6 | V p-p |
Input Common-Mode Range | 1.1 V to AVDD | V |
High Level Input Voltage | 1.2 to 3.6 | V |
Key Features
- Dual 14-bit ADCs with sampling rates of up to 150 MSPS.
- Integrated wideband digital downconverter (DDC) with multiple signal processing stages.
- 32-bit frequency translator (numerically controlled oscillator, NCO), half-band decimating filter, fixed FIR filter, and fADC/8 fixed-frequency NCO.
- Fast overrange detect and signal monitor functions for automatic gain control (AGC).
- Programmable threshold detector for monitoring incoming signal power.
- Integrated voltage reference and duty cycle stabilizer for ADC clock duty cycle compensation.
- Support for CMOS, LVDS, and LVPECL logic compliance for differential clock inputs.
- Lead-free and RoHS-compliant 64-LFCSP package.
Applications
- Communications systems, including GSM, EDGE, and CDMA.
- Intermediate frequency (IF) receiver applications requiring high-speed ADCs and integrated signal processing.
- Systems needing low cost, small size, and high versatility.
- Automatic gain control (AGC) systems benefiting from fast overrange detection and signal monitoring.
Q & A
- What is the resolution of the AD6655BCPZ-150 ADCs?
The AD6655BCPZ-150 features dual 14-bit ADCs.
- What are the sampling rates supported by the AD6655BCPZ-150?
The AD6655BCPZ-150 supports sampling rates of up to 150 MSPS.
- What type of signal processing stages are integrated in the AD6655BCPZ-150?
The AD6655BCPZ-150 includes a 32-bit frequency translator (NCO), a half-band decimating filter, a fixed FIR filter, and an fADC/8 fixed-frequency NCO.
- Does the AD6655BCPZ-150 have built-in functions for automatic gain control (AGC)?
Yes, it includes fast overrange detect and signal monitor functions to aid in AGC.
- What is the package type and compliance of the AD6655BCPZ-150?
The AD6655BCPZ-150 is packaged in a 64-LFCSP and is lead-free and RoHS-compliant.
- What are the typical applications for the AD6655BCPZ-150?
It is used in communications systems such as GSM, EDGE, and CDMA, and in IF receiver applications requiring high-speed ADCs and integrated signal processing.
- What is the logic compliance of the differential clock inputs on the AD6655BCPZ-150?
The differential clock inputs comply with CMOS, LVDS, and LVPECL logic standards.
- How does the AD6655BCPZ-150 handle variations in the ADC clock duty cycle?
The AD6655BCPZ-150 includes a duty cycle stabilizer to compensate for variations in the ADC clock duty cycle.
- What is the purpose of the integrated voltage reference in the AD6655BCPZ-150?
The integrated voltage reference eases design considerations and ensures stable ADC performance.
- Can the AD6655BCPZ-150 monitor the composite magnitude of the incoming signal?
Yes, the signal monitor function allows monitoring of the composite magnitude of the incoming signal to optimize system gain.