Overview
The AD6655ABCPZ-80, produced by Analog Devices Inc., is a mixed-signal intermediate frequency (IF) receiver. It features dual 14-bit analog-to-digital converters (ADCs) with sampling rates of 80 MSPS, 105 MSPS, 125 MSPS, and 150 MSPS. This device is designed to support communications applications where low cost, small size, and versatility are crucial. The AD6655 includes a wideband digital downconverter (DDC) and is optimized for applications requiring high performance and flexibility.
Key Specifications
| Parameter | Unit | Min | Typ | Max |
|---|---|---|---|---|
| Resolution | Bits | 14 | 14 | 14 |
| Offset Error | % FSR | ±0.2 | ±0.6 | ±0.6 |
| Gain Error | % FSR | −3.6 | −1.8 | −0.1 |
| Temperature Drift - Offset Error | ppm/°C | ±15 | ±15 | ±15 |
| Temperature Drift - Gain Error | ppm/°C | ±95 | ±95 | ±95 |
| Internal Voltage Reference Output Voltage Error (1 V Mode) | mV | ±5 | ±18 | ±18 |
| Signal-to-Noise Ratio (SNR) at fIN = 2.4 MHz | dB | 73.0 | 74.9 | 74.9 |
| Differential Clock Input Voltage Range | V p-p | 0.2 | 6 | 6 |
Key Features
- Dual 14-bit ADCs with sampling rates of 80 MSPS, 105 MSPS, 125 MSPS, and 150 MSPS.
- Wideband digital downconverter (DDC) integrated with the ADCs.
- Multistage, differential pipelined ADC architecture with integrated output error correction logic.
- Wide bandwidth differential sample-and-hold analog input amplifiers with user-selectable input ranges.
- Integrated voltage reference to simplify design considerations.
- Duty cycle stabilizer to compensate for variations in the ADC clock duty cycle.
- Four cascaded signal processing stages in each receive channel: a 32-bit frequency translator, a half-band filter, a FIR filter, and a decimation stage.
Applications
The AD6655ABCPZ-80 is designed for various communications applications, including:
- Wireless communication systems.
- Radar systems.
- Medical imaging equipment.
- Test and measurement instruments.
- High-speed data acquisition systems.
Q & A
- What is the resolution of the ADCs in the AD6655ABCPZ-80?
The ADCs in the AD6655ABCPZ-80 have a resolution of 14 bits.
- What are the sampling rates supported by the AD6655ABCPZ-80?
The AD6655ABCPZ-80 supports sampling rates of 80 MSPS, 105 MSPS, 125 MSPS, and 150 MSPS.
- What type of digital downconverter is integrated with the ADCs?
The AD6655ABCPZ-80 features a wideband digital downconverter (DDC).
- Does the AD6655ABCPZ-80 have an integrated voltage reference?
Yes, the AD6655ABCPZ-80 includes an integrated voltage reference.
- What is the purpose of the duty cycle stabilizer in the AD6655ABCPZ-80?
The duty cycle stabilizer compensates for variations in the ADC clock duty cycle to maintain excellent performance.
- How many signal processing stages are in each receive channel of the AD6655ABCPZ-80?
Each receive channel has four cascaded signal processing stages.
- What are some common applications of the AD6655ABCPZ-80?
The AD6655ABCPZ-80 is used in wireless communication systems, radar systems, medical imaging equipment, test and measurement instruments, and high-speed data acquisition systems.
- What is the temperature range for the AD6655ABCPZ-80?
The AD6655ABCPZ-80 operates over a temperature range of −40°C to +85°C.
- What package type is the AD6655ABCPZ-80 available in?
The AD6655ABCPZ-80 is available in a 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ).
- What is the signal-to-noise ratio (SNR) of the AD6655ABCPZ-80 at fIN = 2.4 MHz?
The SNR at fIN = 2.4 MHz is approximately 74.9 dB.
