Overview
The AD6636CBCZ, produced by Analog Devices Inc., is a 150 MSPS Wideband Digital Downconverter (DDC) designed for direct IF sampling or highly sampled baseband radios. This component is optimized for the demanding filtering requirements of wideband standards such as CDMA2000, UMTS, and TD-SCDMA, and is flexible enough to support wider standards like WiMAX. The AD6636 is part of radio systems that use either an IF sampling ADC or a baseband sampling ADC, providing advanced signal processing capabilities.
Key Specifications
| Specification | Details |
|---|---|
| Sampling Rate | Up to 150 MSPS per input port; up to 300 MSPS with external interface logic |
| Input Ports | Four single-ended or two LVDS parallel input ports (16-bit mantissa + 3-bit exponent) |
| Output Ports | Three 16-bit parallel output ports operating at up to 200 MHz |
| Signal Processing Stages | Frequency translator, 5th order cascaded integrated comb filter, cascaded fixed-coefficient FIR and half-band filters, three cascaded programmable coefficient sum-of-product FIR filters, interpolating half-band filter (IHB), and digital AGC block |
| Clocking and Interfaces | Internal PLL clock multiplier, serial or microport interfaces for programming and control |
| Package | 256-Ball CSPBGA (17mm x 17mm) |
| Operating Temperature | -40°C to +85°C |
| Input Data Format | 16-bit mantissa and 3-bit exponent (floating-point or fixed-point) |
Key Features
- Six independent wideband processing channels capable of processing wideband carriers.
- Quadrature correction and DC correction for complex inputs.
- RMS/Peak power monitoring of input ports.
- Programmable attenuator control for external Digital Variable Gain Amplifier (DVGA).
- Three programmable coefficient FIR filters per channel.
- Interpolating half-band filter per channel to increase output rate.
- Digital Automatic Gain Control (AGC) block for output data scaling.
- Internal test signal (PN pseudorandom noise sequence) for Built-In Self-Test (BIST).
- High speed signal-level detection, gain control, and quadrature I/Q correction.
Applications
The AD6636CBCZ is designed for use in radio systems that require advanced signal processing, particularly in:
- Direct IF sampling or highly sampled baseband radios.
- Wideband standards such as CDMA2000, UMTS, TD-SCDMA, and WiMAX.
- Baseband and IF sampling ADC systems.
- Wireless communication infrastructure, including base stations and repeaters.
Q & A
- What is the maximum sampling rate of the AD6636CBCZ?
The AD6636CBCZ can sample at up to 150 MSPS per input port, and up to 300 MSPS with external interface logic using two input ports and two internal channels processing in tandem.
- How many input ports does the AD6636CBCZ have?
The AD6636CBCZ has four single-ended or two LVDS parallel input ports.
- What is the format of the input data for the AD6636CBCZ?
The input data format is 16-bit mantissa and 3-bit exponent, supporting both floating-point and fixed-point inputs.
- What signal processing stages are included in the AD6636CBCZ?
The AD6636CBCZ includes a frequency translator, 5th order cascaded integrated comb filter, cascaded fixed-coefficient FIR and half-band filters, three cascaded programmable coefficient sum-of-product FIR filters, an interpolating half-band filter (IHB), and a digital AGC block.
- How is programming and control of the AD6636CBCZ accomplished?
Programming and control are accomplished via serial or microport interfaces.
- What is the operating temperature range of the AD6636CBCZ?
The operating temperature range is -40°C to +85°C.
- What type of package does the AD6636CBCZ come in?
The AD6636CBCZ comes in a 256-Ball CSPBGA package (17mm x 17mm).
- Does the AD6636CBCZ support internal test signals for Built-In Self-Test (BIST)?
Yes, the AD6636CBCZ supports an internal test signal (PN pseudorandom noise sequence) for BIST.
- What is the purpose of the digital AGC block in the AD6636CBCZ?
The digital AGC block is used for output data scaling.
- Can the AD6636CBCZ support multiple clocking modes?
Yes, the AD6636CBCZ supports multiple modes for clocking data into and out of the chip, providing flexibility for interfacing to various digitizers.
